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Reports until 13:01, Tuesday 17 January 2023
H1 SUS (CDS, CSWG, DetChar, OpsInfo)
jeffrey.kissel@LIGO.ORG - posted 13:01, Tuesday 17 January 2023 (66836)
Jan 2023 Inventory of 20-, 18-, and 16-bit DACs on H1 SUS Actuator Stages
J. Kissel

Here's an inventory of which isolation stage of which SUS use which bit DAC at LHO as of 2022-Jan-17.

20-bit DACs
    QUADS:
        - ETMs: L1 (UIM), L2 (PUM), L3 (TST) stages
        - ITMs: L2 (PUM), L3 (TST) stages
    TRIPLES:
        - BS: M2 stage
        - SRM & SR2: M2, M3 stages
        - FC1 & FC2: all stages: M1, M2, and M3

16-bit DACs
    DOUBLES: 
        - All ZM M1: stages
        - ZM2, ZM4, & ZM5 M2 "fast" PZT drives
        - ZM1, ZM3 M2 DCOIL drives
    SINGLES:
        - OM1 and OM3
        - All RMs
        - OPO
        - OFI

Beckhoff DACs
    TRIPLES:
        - SR3 M3 thermal actuator on ROC
    DOUBLES:
        - OM2 M2 thermal actuator on ROC
         
18-bit DACs
Every other stage / actuator that's not mentioned above.


This configuration is/was chosen to upgrade the actuators which are most critical to IFO noise performance, as best we know, in the face of limited DAC supply to date. As new DACs role in, and 18-bit DACs fail, they will be slowly but surely upgraded, as per ECR E2100485 / IIET Ticket 20828. Those suspensions which have 16-bit DACs have already been deemed less critical for noise performance, and 16-bit DACs are often used for their higher channel count, so it's likely they'll remain 16-bit DACs. 
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