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Reports until 16:31, Wednesday 14 January 2026
LHO General
corey.gray@LIGO.ORG - posted 16:31, Wednesday 14 January 2026 (88760)
Wed DAY Ops Summary

TITLE: 01/14 Day Shift: 1530-0030 UTC (0730-1630 PST), all times posted in UTC
STATE of H1: Planned Engineering
INCOMING OPERATOR: None
SHIFT SUMMARY:

Today's big activities:  JAC alignment continues  at HAM1.  SUS model/daq work continues from Control Room and CER.  HAM7 squeezer alignment continues.
LOG:

H1 SUS
oli.patane@LIGO.ORG - posted 14:54, Wednesday 14 January 2026 (88766)
SUS-C1 and SUS-C6 AI Chassis Modified, SUS-C2 Modified AI Chassis Installed

Marc, Jeff, Fil, Oli

Yesterday we pulled most of the AI chassis (D1000305 or D1600077) from SUS-C1 and SUS-C6, modified them for ECR E2400409 and E2500296 (IIET 35739 and 35706, respectively), and reinstalled them as part of our work converting SUSB123 and SUSH34 into SUSB13 and SUSB2H34 (88765). 

Every AI chassis in SUS-C1 and SUS-C6 was meant to be pulled, upgraded, and reinstalled EXCEPT SUS-C1 U24. Additionally, we needed to also modify a spare D1000305 AI chassis for installation into SUS-C2. We did all this, but along the way we accidentally also pulled and upgraded the AI chassis in SUS-C1 U24 (previously S1104380). Luckily, we hadn't modded the spare (S2100712) yet so we installed it into SUS-C1 U24 and installed that modified chassis in the SUS-C2 U14 spot.

Here are the steps for how we modified the AI chassis:
- Disconnected all affected AI output cables in SUS-C1 and SUS-C6
- Removed the existing 6x 2x 8CH DAC AI chassis (D1000305 or D1600077),
- Modified them to become D2500353 1x 32CH AI chassis 
    . Replaced the 2x 8CH AI rear panel with WD relays (D1000551) with 1x 32CH AI rear panel without WD relays (D2500097)
    . Replaced the 2x 8CH back panel (D1000552 with 1x 32CH back panel (D2400308)
- Relabeled AI chassis from D1000305 to D2500353, or from D1600077 to D2500397, and reinstalled
- Cabled everything up according to the corresponding version of the wiring diagram (SUSB13, SUSB2H34)

Pulled, upgraded, and reinstalled:
                                            D1000305 > D2500353     D2500097
SUS Chain               Rack / Position     Chassis S/N             Rear Board S/N     32CH DAC Card / IO Slot    Channels

ITMY M0/R0/L1           SUS-C6 / U38        S1108073                S2501317           DAC0 / Slot#2              0-15

ITMX M0/R0/L1           SUS-C6 / U37        S1108072                S2501319           DAC0 / Slot#2              16-31

ITMY L2, ITMX L2        SUS-C6 / U35        S1108074                S2501316           DAC1 / Slot#4              0-15

MC2 M1,PR2 M1,SR2 M1    SUS-C1 / U31        S1104379                S2501321           DAC2 / Slot#5              0-15

SR2 M1, MC2 M2/M3       SUS-C1 / U30        S1104368                S2501320           DAC2 / Slot#5              16-31

                                            D1600077 > D2500397
                                            Chassis S/N

ITMX ESD, ITMY ESD      SUS-C6 / U21        S1600245                S2501318           DAC1 / Slot#4              16-27

Upgraded and newly installed (technically was pulled from SUS-C1 U24 by accident):
BS M1/M2                SUS-C2 / U14        S1104380                S2501322           DAC3 / Slot#6              0-11

 

NOT upgraded but chassis swapped:
                                                    D1000305              D1000305
SUS Chain                        Rack / Position    Chassis S/N Before    Chassis S/N Now    

PR2 M2, PR2 M3, SR2 M2, SR2 M3   SUS-C1 / U24       S1104380              S2100712

H1 SUS (CDS, IOO, ISC, SUS)
jeffrey.kissel@LIGO.ORG - posted 14:09, Wednesday 14 January 2026 (88765)
CER Hardware/Electronics Changes To Convert SUSB123 and SUSH34 to SUSB13 and SUSH34 Complete; User Model Software Changes Commencing
J. Kissel, F. Clara, O. Patane, M. Pirello, D. Barker
ECR E2500296, E2400409
WP 12962
D2300401 (for susb13) and D2300383 (for susb2h34)
G2301306 -- PARTII 2023 plan, PARTII Update 

We've completed all electronics hardware moves, cabling/recabling and new installations that we plan to do on SUS MC2, PR2, SR2, BS, and the future LO1 and LO2 for now.

Given that this change to the electronics is somewhere in between versions of the D2300401 h1susb13 and D2300383 h1susb2h34 wiring diagrams -- the interim configuration we're in now that 

    Does have
        - susb2h34 and susb13, as well as susauxb13 and susauxb2h34 with all their ADC and DAC cards, as they will be in O5.
        - All of the BS electronics have been moved from SUS-C5/SUS-C6 to SUS-C1/SUS-C2, and their CER cabling dragged along with it
        - all AI chassis driven by 28-bit 32CH DACs (7 in total) have been converted from a pair of D1000305 2x8CH DAC AIs to a pair of D2500353 1/2x32CH DAC AIs.
        - ITM AA chassis inputs (both OSEM sensors, optical levers, and CD monitors) and AI chassis outputs have been re-arranged such that the grouping is far more sensibly arranged and modular per QUAD.
    
    Doesn't have 
        - BBSS-like BS TOP mass converted to QOSEMs
        - BBSS-like BS M3 OSEM sensing and actuation electronics
        - Any LO1 or LO2 electronics
        - The BS optical lever in its final AA chassis position (because the BS TOP mass OSEMs still need that spot)
        
        - Any changes to the field cabling
            - the BS M1 satamps, M2 satamps, and M3 optical lever whitening chassis are all still in SUS-R6)
-- we planned /documented all of this work on google slides -- see PARTII Update -- which is linked in the abstract of G2301306.

We'll add more details, gotchas, and pictures below in the comments.
LHO VE
david.barker@LIGO.ORG - posted 10:52, Wednesday 14 January 2026 (88764)
Wed CP1 Fill

Wed Jan 14 10:10:16 2026 INFO: Fill completed in 10min 12secs

 

Images attached to this report
H1 CDS
david.barker@LIGO.ORG - posted 07:38, Wednesday 14 January 2026 (88761)
CDS BS move and LIGO-DAC upgrade

Fil, Marc, Richard, Jeff, Oli, Erik, EJ, Jonathan, Dave:

WP12962 Move BS for upgrade to BBSS. WP12901 Upgrade ITM to LIGO-DAC

On Tuesday 13Jan2026 we reconfigured the BSC1,2,3 and HAM3,4 suspensions to move the BS control from h1susb123 to h1sush34 and upgrade the ITM test mass suspensions to use the new LIGO-DACs. Associated changes were also made to these systems' SUS-AUX frontends.

Frontend Computer Renaming:

old name new name
h1susb123 h1susb13
h1sush34 h1susb2h34
h1susauxb123 h1susauxb13
h1susauxh34 h1susauxb2h34

Prep Work:

The 4 LIGO-DACs used for this upgrade were calibrated in the EE shop and FE tested on the DTS.

The EDC was moved from h1susauxb123 to h1susauxh56

Upgrade:

The h1susb123 and h1sush34 suspensions were SDF reconcilled and put into their safe state.

The SWWD seismic systems were put into an infinite bypass.

All 4 front end were powered down and work on their IO Chassis, AAs and AIs started.

h1susb13 IO Chassis

8 20bit-DACs removed, 2 LIGO-DACs added.

Removed 20bit-DACs

20bit-DAC 18/20bit-DAC Interface Card
200217-17 S1200228
220218-29 S1200227
210303-49 S1200224
210303-35 S1200219
210303-22 S1200220
200217-19 S1200221
210303-57 S1200226
220218-08* S1200229

* 20bit-DAC 220218-08 installed in new h1susb2h34 chassis.

New Adnaco Layout

Adnaco slot Card [interface]   Adnaco slot Card [Interface]
A1-1 LIGO Timing Card   A3-1 empty
A1-2 empty   A3-2 empty
A1-3 ADC0 (orig)   A3-3 empty
A1-4 LIGO-DAC0 S2500457 [010]   A3-4 empty
         
A2-1 ADC1 (origin)   A4-1 BIO0 (orig)
A2-2 LIGO-DAC1 S2500448 [011]   A4-2 BIO1 (orig)
A2-3 empty   A4-3 BIO2 (orig)
A2-4 empty   A4-4 empty

h1susauxb13 IO Chassis

Removed last 2 ADCs, installed them in h1susauxb2h34 IO Chassis. ADC count went from 8 to 6.

h1susauxb2h34 IO Chassis

Added the 2 ADCs from h1susauxb13 in next available slots. ADC count went from 6 to 8.

ADC ADC Card Interface Card
ADC6 110128-11 S1102417
ADC7 110128-03 S1301433

h1susb2h34 IO Chassis

Original layout skipped Adnaco slot A2-4. Reviewed as-built drawings and alog but could not find why this slot was not being used. Assuming that there was something wrong with this slot I replaced the second Adnaco backplane

Suspect Backplane (removed) C8610415
New Backplane (installed) C8610796

Original layout was:

2 ADC, 5 18bit-DAC, 1 20bit-DAC, 2 BIO.

Update: keep the 2 ADCs, remove all 5 18bit-DACs, keep the 1 20bit-DAC and add a second 20bit-DAC, add 2 LIGO-DACs and add a third BIO.

Table of removed 18bit-DACs + IF

18bit-DAC Interface Card
110425-10 S1104013
101208-71 S1104017
110425-04 S1104014
110425-09 S1104023
110425-46 *

* Because the 18bit and 20bit DACs use the same Interface card, this IF card was left in the chassis for the second 20bit-DAC

New Adnaco layout

Adnaco slot Card [Interface]   Adnaco slot Card [Interface]
A1-1 LIGO Timing Card   A3-1 empty
A1-2 empty   A3-2 empty
A1-3 ADC0 (orig)   A3-3 empty
A1-4 20bit-DAC0 (orig)   A3-4 empty
         
A2-1 ADC1 (orig)   A4-1 BIO0 (orig)
A2-2 20bit-DAC1 *   A4-2 BIO1 (orig)
A2-3 LIGO-DAC0 S2500454 [012]   A4-3 BIO2 ADRBS96001188
A2-4 LIGO-DAC1 S2500442 [013]   A4-4 empty

* 20bit-DAC1 ss0218-08 repurposed from h1susb123 surplus.

Timing Card Firmware Upgrade (Marc)

All 4 IO Chassis Timing Cards had a firmware upgrade. This was essential for the control frontends, which would not be able to drive the LIGO-DACs without the new firmware. The SUS-AUX TCs were upgraded as part of the general upgrade of all frontends.

  Tming Card Firmware Version
old 1 - 0x1f0
new 2 - 0x635

 

Model Changes and Current Status

h1iopsusb13 New model name, installed but needs SWWD review
h1susitmx Not running, being reworked
h1susitmy Not running, being reworked
h1susitmpi Not running, being reworked
h1iopsusb2h34 New model name, installed but needs SWWD review
h1susbs New location, not running, being reworked
h1susmc2 Not running, being reworked
h1suspr2 Not running, being reworked
h1sussr2 Not running, being reworked
h1iopsusauxb13 New model name, running and complete
h1susauxb13 Temporary model running, being reworked
h1iopsusauxb2h34 New model name, running and complete
h1susauxb2h34 Temporary model running, being reworked

All models are being built with RCG5.5.2, which is needed to drive more than 1 LIGO-DAC.

LHO General
corey.gray@LIGO.ORG - posted 07:37, Wednesday 14 January 2026 - last comment - 08:13, Wednesday 14 January 2026(88759)
Wed DAY Ops Transition

TITLE: 01/14 Day Shift: 1530-0030 UTC (0730-1630 PST), all times posted in UTC
STATE of H1: Planned Engineering
OUTGOING OPERATOR: None
CURRENT ENVIRONMENT:
    SEI_ENV state: MAINTENANCE
    Wind: 6mph Gusts, 4mph 3min avg
    Primary useism: 0.03 μm/s
    Secondary useism: 0.45 μm/s 
QUICK SUMMARY:

Foggy morning on site where the LVEA continues to be in Laser HAZARD for in-chamber work at HAM1 & HAM2.  

MuseumEXP continues with new-exhibit work at LExC this week.

Comments related to this report
corey.gray@LIGO.ORG - 08:13, Wednesday 14 January 2026 (88762)

My last shift was in 2025.  Some notes:

  • HAM1 ISI WD tripped 8-days ago--assuming for JAC in-chamber work (updated white board)
  • BSC 1/2/3 OFFLINE  (updated white board)
  • Too foggy to check arms for tumbleweeds with cameras.
  • Dust Monitor LAB2 has a "not a number" ERROR, all others OK/correct.
H1 IOO (ISC)
jennifer.wright@LIGO.ORG - posted 18:38, Tuesday 13 January 2026 - last comment - 18:46, Tuesday 13 January 2026(88757)
Locking JAC in air

Jennie W, Masayuki N

 

Daniel set up some model changes last week in h1lsc to allow us to use the JAC-TRANS_A DCPD to lock the cavity. This is a workaround of what is intended to be the normal operation where the locking is done with the JAC-REFL_A PD on IOT1. Rolling this table up to the chamber would make it hard to install the optics on that side of the table so we need this workaround to see the beam transmitted through the cavity that we can use to align the beam from JAC into the IMC.

This PD is just a DC PD so we cannot use PDH to lock as we would for the REFL PD. Yesterday and today Masayuki and I worked on an offset lock, where we use the transmitted power offset to the side of the fringe after normalising the error signal by the maximum transmitted power on resonance.

Use JAC Overview->DITHER. The demodulation is set up so the SIN gain is one and connects to I filter bank which also has a gain of 1. Q filter bank is terminated at the output.

First step is to use the ramp on JAC Overview -> JAC-PZT_Driver by pressing "ENABLE" in right-hand corner, the slider on the left side needs to be near -10V for this to work. Measure the max peak height of the TM00 mode - transmitted power off resonance.

The normalisation is done using the high pass filter bank block at the left of the screen, this opens up H1JAC-DITHER_PD_IN. The gain should be set to the normalisation constant, 1/(transmitted power on resonance - transmitted power off resonance).

The actual servo shaping is done using H1JAC-DITHER_SERVO, which is linked on the right of the 'DITHER' screen. Set the offset to -0.6 to shift the normalised error signal so the zero crossing is just below halfway up the fringe. Check the input and output of the filter bank after the servo are turned on, this is linked on the right of the 'DITHER' screen and is called 'PZT'.

Make sure the PZT ramping is turned off by pressin 'DISABLE on the  JAC-PZT_Driver screen.

Turn on the UGF100 and LP10 filters in the 'H1JAC-DITHER_SERVO' filter bank. These have a gain of 3000 and a low pass filter which rolls off at 10Hz respectively. This latter one is to invert the PZT response.

The gain in this filter bank should be on, use the slider on the 'DITHER' screen to tune to a TM00 peak and then turn on the servo output. Once locked you can turn on the Int1Hz filter to add an integrator below 1Hz and the boost to give an extra 5x gain.


For a better lock we also implemented a proper DITHER SERVO.

The dither frequency is set to 2.5KHz and the demod phase is set at 0 degrees. The input signal no longer had normalisation in H1JAC-DITHER_PD_IN as the error signal will now be the beat between the PZT dither and the cavity transmitted power and so has a zero crossing at the centre of resonance.

There is a high pass filter in  H1JAC-DITHER_PD_IN to avoid up-conversion of noise below 1 kHz. After the demodulation both 'I' and "Q' filter banks have a low pass filter at 1kHz to prevent 2.5kHz and harmonics from getting magnified by the loop.

Both I and Q phase now have a low pass filter at 1KHz to prevent harmonics of the dither frequency appearing in the error signal. The locking technique is the same after this point as the filters needed in the 'SERVO' block do not change as the actuator response has not changed.

Masayuki has set up both these locking processes in the JAC guardian but this is still WIP.

 

Images attached to this report
Comments related to this report
jennifer.wright@LIGO.ORG - 18:46, Tuesday 13 January 2026 (88758)
Images attached to this comment
H1 SEI
jim.warner@LIGO.ORG - posted 17:55, Tuesday 13 January 2026 (88756)
Power supply at EX failed killing EX ISI cps timing

RyanS told me yesterday that he could re-isolate the ETMX ISI. I finally got to looking at it today and something was off with the CPS. Using the weekly CPS spectra script I got ASDs for the CPS from last night and a bunch of the the CPS spectra were way off, first image.

I went to EX and looked at racks, SEI chassis all looked fine. I unplugged a couple of CPS probes at the chamber and did not get the expected behavior. One CPS went to the near limit rail (-32k) the others hardly changed at all. This made me suspect timing, so I traced out the timing sync wires, found the 71Mhz CPS timing fanout and the lights were all off. Looked at the power strip and only the -18v led was on. Turned off the fanout chassis, took some pics and found Marc and Fil.

Marc came to the end and we looked at power supplies in the front of the building and the +18 for the rack was dead. We swapped both power supplies for spares, and CPS timing seems to have come back, I was able to isolate the ISI. Marc said the fans seemed a bit stiff and smelled weird, so maybe another fan failure.

Images attached to this report
H1 AOS
marc.pirello@LIGO.ORG - posted 17:32, Tuesday 13 January 2026 (88755)
Replaced Kepco Supplies EX, ISC-R1 +/- 18V

Per WP12970

ISC-R1 +18V supply failed this afternoon.  This set was slated for replacement, so we replaced both legs.

+18V S1300287 was replaced with S1202002 with new ball bearing fan installed.
-18V S1300275 was replaced with S1201995 with new ball bearing fan installed.

M. Pirello, J. Warner

LHO VE
david.barker@LIGO.ORG - posted 17:00, Tuesday 13 January 2026 (88754)
Tue CP1 Fill

Tue Jan 13 10:09:38 2026 INFO: Fill completed in 9min 34secs

 

Images attached to this report
LHO General
ryan.short@LIGO.ORG - posted 16:33, Tuesday 13 January 2026 (88753)
Ops Day Shift Summary

TITLE: 01/14 Day Shift: 1530-0030 UTC (0730-1630 PST), all times posted in UTC
STATE of H1: Planned Engineering
INCOMING OPERATOR: None
SHIFT SUMMARY: Another busy day of upgrades; JAC installation and HAM7 beam alignment continued while the move/upgrade of BS DACs began today and should wrap up tomorrow morning. Jim also discovered a failed power supply at EX which looks to be the reason the chamber can't be recovered, so he and Marc are starting to take action there.
LOG:                                                                                                                                           

Start Time System Name Location Lazer_Haz Task Time End
---- SAF HAZARD LVEA YES LVEA is Laser HAZARD Ongoing
16:27 FAC Kim, Nellie LVEA - Technical cleaning 17:18
16:41 CDS Marc, Fil, Oli CER - SUS computer upgrades 20:22
16:49 CDS Jeff CER - SUS computer upgrades 21:04
16:49 CAL Tony PCal Lab Local Check measurement 20:17
17:01 JAC Rahul LVEA Y JAC installation 19:42
17:24 SQZ Sheila, Elenna, Kar Meng LVEA Y HAM7 SQZ beam alignment 18:25
17:27 JAC Jennie LVEA Y Opening light pipe 17:33
18:30 CDS Dave CER - susb123 DAC upgrades 22:33
18:32 JAC Masayuki LVEA Y JAC installation 19:42
18:55 SQZ Elenna LVEA - Replacing viewport cover 19:07
18:56 VAC Gerardo EX N Troubleshoot AIP 19:36
18:57 FAC Kim EX N Technical cleaning 19:36
19:24 FAC Tyler, MacMiller FCES N Air handler work 22:33
20:01 CDS Richard CER - Checking progress 20:30
20:22 CDS Fil MY N Picking up cables 23:09
20:22 CDS Oli CER - SUS computer upgrades 21:05
21:11 VAC Gerardo EX N Troubleshoot AIP 21:30
21:13 CAL Tony PCal Lab Local Getting serial numbers 00:08
21:17 VAC Travis LVEA - Looking for parts 21:24
21:45 CDS Jeff CER - SUS computer upgrades 00:18
21:51 JAC Jennie, Rahul LVEA Y JAC installation, Rahul out @ 22:47 01:25
22:10 JAC Masayuki LVEA Y JAC installation 01:25
22:24 CDS Oli CER - SUS computer upgrades 01:11
22:35 JAC Betsy LVEA - Check on JAC progress 22:47
22:35 JAC Keita LVEA - JAC installation 01:25
22:35 PEM RyanC CER - Grabbing DM stand 22:38
22:54 CDS Marc MY N Getting parts 23:11
23:10 CDS Fil CER - SUS computer upgrades 01:10
23:23 SQZ Sheila LVEA Y Opening HAM7 viewport cover 23:29
23:52 SEI Jim EX N Checking electronics 00:25
00:02 VAC Travis Mids N Looking for parts 00:31
H1 SQZ
sheila.dwyer@LIGO.ORG - posted 16:31, Tuesday 13 January 2026 (88751)
HAM7 early part of this week

Sheila, Kar Meng, Elenna, Jim

Yesterday Jim and I went to the chamber in the morning to work on cables. We got a solution for the cables after some work, but one peek zip tie luanched itself across the chamber.  We spent a few hours searching for this; I climbed into the chamber on the -X side and could them see it on the bottom of the +Y door where Jim was able to reach through the port and retreive it.  

In the afternoon Kar Meng and I went back to the chamber and found that the beam was blocked on the cable clamp that Jim and I had added earlier.  The previous cable routing is shown here, the peek cable clamp is on the bottom of the pillar so that it doesn't block the beam.  We removed the new alumium clamp and I tried to move it lower, the second from the top bolt hole is not the right size so we need to place this in the 3rd from the top hole.  I found that difficult to reach and eventually decided to leave it for another day or ask for help from someone with longer reach.  

After this we saw that our beam did arrive on AS_C in HAM6 but wasn't aligned onto AS_A or AS_B.  

This morning Elenna, Kar Meng and I went to the chamber to see if we could improve the alignment.  We walked B:M3 to align onto the second iris on SQZT7, and B:M4 to align onto the iris in front of ZM4, which seems degenerate with the iris at the bottom of the SQZT7 periscope.  This worked well and we could see light on AS_B and AS_C although nothing on AS_A.  We then went to the control room and moved ZM6 to center on AS_C better, then we could engage the AS centering loops.  

This afternoon Kar Meng and I had another look at alignment from the control room.  We have set the OMs back to their alignments during the run, and we still have the beams on AS_C, AS_A and AS_B although we are using a lot of the range on ZM6.  

Still to do before finishing in HAM7:

H1 AOS
rahul.kumar@LIGO.ORG - posted 13:35, Tuesday 13 January 2026 - last comment - 16:22, Tuesday 13 January 2026(88748)
HAM1 update - added some lenses and mirrors for JAC

Masayuki, Jennie, Rahul

Given below are the list of lenses and mirrors I have placed on the ISI table and roughly positioned (without the beam for now) them as per following drawings  - D2500344 and D0901821.

Lenses - L1, L2 and L3: Masayuki confirmed from the vendor that the arrow mark on the lens point towards the convex side. For lens L1, arrow is pointing against the PEEK ring (in the lens holder). For Lens L2 and L3 the arrow is pointing towards the PEEK ring. The PEEK ring for all three lens are facing towards the HAM2 chamber. In other words, curved surface of L1 is facing towards the PSL and for L2-3 towards HAM2.

I re-cleaned L1 lens after finding some dust particles on the curved surface, post cleaning the lens looked better.

Reflecting mirrors - JAC-RM1, JAC-RM2, JM2 and M3.

Masayuki and I also added a temporary Siskyou mount acting as JM3 (for Tip Tilt, just like JM1). We will replace both of them with the Tip Tilt next week.

Next, we proceed with aligning/pointing the above optics with the beam. L1 and JM2 are already decently pointing (although without a locked JAC) towards JM3.

Comments related to this report
rahul.kumar@LIGO.ORG - 16:22, Tuesday 13 January 2026 (88749)

Pictures attched from HAM1 chamber.

Images attached to this comment
H1 SUS (CDS, SEI)
jeffrey.kissel@LIGO.ORG - posted 08:45, Tuesday 13 January 2026 - last comment - 16:20, Tuesday 13 January 2026(88745)
H1SUSB123 and H1SUSH34 SUS and SEI Systems prepped in SAFE for Conversion to SUSB13 and SUSH34
J. Kissel
ECR E2500296, E2400409
WP 12962

D2300401 (for susb13) and D2300383 (for susb2h34)

We begin the major upgrade of the H1SUSB123 and H1SUSH34 SUS and SEI Systems converting them to SUSB13 and SUSH34 a la G2301306 today. We're focusing on upgrading the DACs in the IO chassis () and all the downstream surrounding impact of that  analog electronics This will take down the following computers, and they will be resurrected with new names as follows:
    FORMER NAME           FORMER SUS              NEW NAME           NEW SUS
    h1susb123             ITMX, ITMY, BS          h1susb13           ITMX, ITMY
    h1sush34              MC2, PR2, SR2           h1susb2h34         BS, MC2, PR2, SR2, LO1, LO2
    h1susauxb123          ITMX, ITMY, BS          h1susauxb13        ITMX, ITMY
    h1susauxh34           MC2, PR2, SR2           h1susauxb2h34      BS, MC2, PR2, SR2, LO1, LO2

As such, I've 
    - brought the ITMX, ITMY, BS, HAM3, and HAM4 SEI systems to ISI_DAMPED_HEPI_OFFLINE (so we don't risk any "hard" trips of HEPI during all this).
    - brought all impacted SUS gaurdians to AUTO mode, then to the SAFE state
    - Increased the bypass time on all impacted software watchdogs to bypass time to a large number (90000000 secs), and hit BYPASS
Comments related to this report
marc.pirello@LIGO.ORG - 16:20, Tuesday 13 January 2026 (88752)

Updated timing cards on newly named SUSB13, SUSB13 AUX, SUSB2H34, SUSB2H34 AUX, formerly known as SUSB123, SUSB123 AUX, SUSH34 and SUSH34 AUX.

Timing FPGA Version 1589

LHO VE (VE)
gerardo.moreno@LIGO.ORG - posted 14:02, Monday 12 January 2026 - last comment - 14:51, Tuesday 13 January 2026(88739)
X2-8 Ion Pump Out of Service

(Travis, Dave, Gerardo)

Dave noted and reported a rise on vacuum pressure at X-End.  Since, Travis and I were in the control room, we quickly determined that the controller for X2-8 ion pump was not working.  I drove down and found the high voltage disabled/off at the controller, and on on the screen the following note:"An excessive arcing condition has been detected (Error10)".  No guidance found on manual, snapped a photo to submit later to vendor.  I restarted the system and the HV started, controller hummed and crackled and was only able to get up to 600 Volts, all while making noise, and one point some funny smell came out of the inside of the controller, HV was disabled, time to replace the unit.

Images attached to this report
Comments related to this report
gerardo.moreno@LIGO.ORG - 14:51, Tuesday 13 January 2026 (88750)VE

(Travis, Gerardo, Richard)

Controller remains off, and high voltage cable is disconnected at both ends, ion pump and controller.

We found a controller for this particular application, and replaced the "old" controller but with similar results, minus the noise.  The controller was only able able to get up to 500 volts and no more.  We turned it off and disconnected the high voltage cable.

I later visited the cable and ion pump to measured them for shorts.  I disconnected the cable from the ion pump, then probed the connector at the controller side, center pin to the shell read 0.808 kOhm, I also probed the center connector to other parts of the cable, but no continuity was read for all cases, including to the conduit.  The ion pump itself was probed for shorts and none was found, at the ion pump connector the center pin was probed to the ion pump body and no continuity was measured.  To compare cables, I measured a "new" cable that we have that is probably half the length of the one in use, no continuity was measured.

I'll wait for the EE guys to have a free moment for them to test the cable.

Images attached to this comment
H1 IOO (IOO)
masayuki.nakano@LIGO.ORG - posted 20:56, Friday 09 January 2026 - last comment - 11:22, Tuesday 13 January 2026(88731)
JAC working log 1/8-9

[Jason, Jennie, Betsy, Keita, Sophie, Masayuki]

Initial alignment (1/8)

 


JAC wiring (1/8)


Wiring confirmation (1/9)


Optics preparation (1/9)

 

Images attached to this report
Comments related to this report
keita.kawabe@LIGO.ORG - 21:59, Friday 09 January 2026 (88732)

Mirrors inspected:

Mirror status was found what was done
M2 Not ready in a lens container with foam sponge after the first cotnact was removed, which is a bad idea. Many dust particles after taking it out of the box. Painted first contact.
M3 Ready Was in the chamber, first contact still on. Removed FC while using top gun. A big dust particle in the back surface, couldn't remove with further top gun, but that's OK.
RM3 Not ready Was in the chamber, first contact still on. Removed FC while using top gun. One dust particle close to the center, couldn't remove. Painted FC.

M3 assy is in the chamber (but is still at the edge of the ISI).

M2 and RM3 optics are stored outside of the chamber.

Lens First Contact problem:

All of the lenses had at least one surface where the first contact was incredibly strongly attached. Simple pulling of the mesh won't do anything even with serious force. We wiggled the mesh in multiple directions with enormous force and the mesh started separating from the FC. Will discuss with Betsy on Monday. All of these are stored outside of the chamber.

L1 FC remains on one surface. Painted FC on top of the existing layer over the mesh. Will see if it makes the FC loose.
L2 FC remains on both surfaces.
L3 FC remains on one surface.

2" Lens Post issue:

All pieces of 8-32 variant of D1000968-v3 were manufactured incorrectly, they have 8-32 bottom screw holes so cannot be mounted on the standard ISC baseplate.

To make them usable, the bottom hole should be widened and re-tapped for 1/4-20 though there's no urgency because we were able to use the original 1/4-20 version. (It seems that this variant was requested on a wrong assumption that Siskiyou lens mount only accepts 8-32. In reality the lens mount has two screw holes, one for 8-32 and the other for 1/4-20, so this variant isn't really needed.)

corey.gray@LIGO.ORG - 11:22, Tuesday 13 January 2026 (88747)EPO

Tagging for EPO photos

H1 SQZ (SQZ)
karmeng.kwan@LIGO.ORG - posted 21:27, Friday 14 November 2025 - last comment - 10:47, Wednesday 14 January 2026(88110)
VOPO measurement setup

Attached is the mode-matching layout for the VOPO. The target primary waist of the VOPO (from TT1700104) is 221.2um(s), 206um(t) for 1064nm and 159.2um(s), 148.8um(t) for 532nm.

The mode matched minor and major beam waist is 198.6um, 204.2um for 1064nm and 152.6um, 185um for 532nm. For the fundamental injection via the rear mirror, the measured waist is 197.25um, 231.85um. These waist is measured at the position marked with a "star". The mode-matching calculation has been reviewed by a fur-low scientist.

Images attached to this report
Non-image files attached to this report
Comments related to this report
karmeng.kwan@LIGO.ORG - 10:47, Wednesday 14 January 2026 (88763)

I have included a diagram showing the components remaining on the optical table, which can be used for testing the homodyne detector.

The attached file also includes the corresponding mode-matching calculation, indicating the resulting beam waist location along the remaining optical path, for future reference.

Non-image files attached to this comment
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