(Keita, Alexa)
We adjusted the phase shifter delay line to 20ns. We optimized this by looking at the X-Y plot of the demod IMON error signal and the PD DC readout (see first picture).
With this phase, and the following common mode board settings, we took an open loop transfer function of the PDH:
- Input 1 gain: -14dB
- Input 1 pol: POS
- Common comp: ON
- Boost 1 stage: ON
- Boost 2 stage: ON
- Fast gain: ON
- Fast pol: POS
- Slow opt: enabled
The OLTF gave a UGF of about 5.6kHz with a phase margin of about 20 deg. I have attached a picture and the data (119 --> mag, 120 --> phase). However, this was not exactly reproducible as the lock kept dropping and the alignment was drifting.
We pulled the PDH common mode board SN S1102632 to make adjustments to the second boost stage as made for EX (see alog 9357). We also pulled the generic interface for the ISC tables (D1002932) SN S1103811 since two out of the four ±12V DC output were not working. Both these units are currently in the EE shop.
We also found a bad connection between the phase modulation panel on ISCTEY and the pockel cell. We reconnected the cable and this seemed to help. We measured the EOM RF power, and found 240mV RMS.
