Reports until 15:43, Tuesday 29 April 2014
H1 SUS (CDS, ISC, SYS)
jeffrey.kissel@LIGO.ORG - posted 15:43, Tuesday 29 April 2014 - last comment - 17:20, Tuesday 29 April 2014(11627)
Alignment Dither Front-End Code Mods for SUS Complete
J. Kissel, D. Barker, J. Batch

I've finished the front-end model modifications for adding independent alignment dither paths, as per ECR E1400105. Today's focus on the BSC suspensions, i.e. the QUADs, the BSFM, and the collateral damage on the TMTS. In addition to adding the dither paths, because I was already modifying top-level, I've cleaned up the ordering of the output ports such that all HAM and BSC SUS types now spit out similar signals in the same order. This includes piping the LOCK control signal out to the top-level model, for the eventual consumption of some auxiliary calibration front end (currently still called OAF) as is already done for the HAM SUS. I've also added any missing SVN $Id$ and $HeadURL$ tags.

When finished, after noticing a peculiar error with the new end-station IPC signals, Dave and Jim reminded me that the different RFM network fabrics for the end-stations require one to add the card number to the IPC part. 
For LHO, EX = card 0, and EY = card 1. 
Last Wednesday, I had incorrectly installed all the RFM IPC parts to both end stations with cardnum=1. This resulted in the two ETMX channels having duplicate IPC numbers, and a receiving error found on the GDS_TP screen. This has now been fixed. It required clearing out all the RFM channels from ASC in the IPC file (/opt/rtcds/lho/h1/chans/ipc/H1.ipc), fixing the card number in the h1asc model, recompiling the sender (h1asc) and the two receivers (h1susetmx, h1susetmy), and a clearing of the RT NET STAT errors by hitting diag reset.

I also terminated the dither inputs to the SIXOSEM_T_STAGE_MASTER library part used in the OMCS_MASTER, which I'd forgotten to do last weekend.

I'll now begin adding this dither path to all SUS MEDM overview screens (and hopefully not uncover any bugs!).

Details:
------------
Affected models:
/opt/rtcds/userapps/release/sus/h1/models
M       h1susbs.mdl
M       h1susetmx.mdl
MM      h1susetmy.mdl
MM      h1susitmx.mdl
MM      h1susitmy.mdl
MM      h1sustmsx.mdl
 M      h1sustmsy.mdl
M       h1susomc.mdl

/opt/rtcds/userapps/release/sus/common/models/
M       BSFM_MASTER.mdl
M       TMTS_MASTER.mdl
M       QUAD_MASTER.mdl
M       OMCS_MASTER.mdl
M       SIXOSEM_F_STAGE_MASTER.mdl

Tips for Stuart:
----------------
- After an svn up of the common/models/ directory, you should only need to make changes to the top-level models.
- The TMTS and OMCS do not need any top level changes, all extra unused ports have been terminated inside the TMTS_MASTER / OMCS_MASTER block, since we know they'll never receive any dither signals.
- Pay close attention to the input and output connections at the top level, especially the lower half of them. This is the only thing you should need to change, but I've added the dither inputs and LOCK outputs in the middle of the input and output list, so most of the lower half of the connections need re-ordering.
- As mentioned above, when adding the RFM IPC to both the ASC and ETM models, be sure to call out the appropriate card number for each end station. You shouldn't need to clear out the IPC file, as long as you don't make the same card numbering error.
Comments related to this report
jeffrey.kissel@LIGO.ORG - 17:20, Tuesday 29 April 2014 (11632)
J. Kissel, D. Barker

I didn't even start *editing* the MEDM screens before I realized I'd forgotten to add any sort of input read-back of the alignment dither signals before they entered the new DITHER2EUL distribution matrix. In *all* of the models, both HAM and BSC SUS. So, I diverted for an hour, installed two new filter banks,
DITHERINF_P
DITHERINF_Y
in the highest level library part (where the dither signal is first digested) in all the core optic masters, 
/opt/rtcds/userapps/release/sus/common/models
M       HSTS_MASTER.mdl
M       QUAD_MASTER.mdl
M       HLTS_MASTER.mdl
M       BSFM_MASTER.mdl
M       MC_MASTER.mdl
and then recompiled, reinstalled, restarted, and restored every model that used it, which includes
h1susmc1
h1susmc2
h1susmc3
h1susprm
h1suspr2
h1suspr3
h1susbs
h1sussrm
h1sussr2
h1sussr3
h1susitmx
h1susitmy
h1susetmx
h1susetmy
Dave rebooted the DAQ / h1dc0 / frame-builder when I finished, around 5:10p PDT. The updated master parts have been committed to the repository.