J. Kissel, R. Abbott

Was checking the status of the ETMX optical lever against Doug's status report (see LHO aLOG 14711) before I took some measurements using it, and found that the ETMX optical lever's compensation filters (i.e. H1:SUS-ETMX_L3_OPLEV_SEG?) have to filters, "gain2" and "gain1.4" (which are gains of 0.5 and 0.707, respectively) that are turned ON. I couldn't find any aLOGs about these filters, and it doesn't really make sense to me to compensate for any analog gain, given that we normalize by the SUM.

Anyone know anything about this?


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Doug's status chart reports values exactly backwards and bit-shifted up 1. "HIGH" bits are LO, and "B1" = B0. The confusion arised from Evan's convention for high vs. low, and that the switches are numbered starting at 0 on the board, and 1 right next to the switch. Therefore, the ETMX is compensated for correctly. 

Will post corrected assessment shortly.


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Piecing together the puzzle, from Doug's aLOG (LHO aLOG 14711), and the various circuit schematics (Configuration Daughter Board D1001631, Chassis Assembly, ), Evan's recent PR3 tune up (LHO aLOG 14631), my aLOG from many moons ago (LHO aLOG 3619), and a phone call to R. Abbott, I can determine that having each channel in the following configuration (as indicated by Doug's aLOG, where B0-B7 is the configuration for the first channel, and the remaining 3 channels, B8-B15, B16-B23, and B24-31 are in the same configuration),
Switch     Function       Setting    Status
 Name                     HI   LO   
  B0      G = 24 [dB]           X      ON
  B1      G = 12 [dB]           X      ON
  B2      G = 6  [dB]      X           OFF
  B3      G = 3  [dB]      X           OFF
  B4      1:10 Whitening        X      ON
  B5      1:10 Whitening   X           OFF
  B6      1:10 Whitening        X      ON
  B7      Latch                 X      ON
Note -- and this seems to be a common misconception -- when the switch is LO (or "0", or away from the chassis as installed) the switch is ON / ENGAGED. Therefore, the total transfer function: G = 36 [dB], two stages of (1:10) whitening.

(filter zero and pole notation is (z:p) -- note that the poles and zeros is INCORRECT [i.e. inverted] in my old aLOG)

Thus, the current compensation scheme, with FM1 (10:1) with FM4 and 5 (the "gain" filters mentioned above), it seems as though the switches have been interpreted in exactly the opposite fashion as the schematic intends. Even worse -- the LATCH is ON, which means it's actually telling the board to engage whatever the settings were *before* the latch were engaged, and the current status of the bits B0 through B7 DON'T MATTER. #facepalm

Will get with Rana / Evan / Doug / Jason about this.