Keith T, Jim, Daniel, Dave
As Keith mentioned in yesterday's CDS meeting, the RFM IPC error rate at the SUS model is related to the CPU usage of the LSC sender. To show this, I've attached a minute trend plot of the past 7 months of IPC error rates at SUS-EX, along with the CPU-MAX of the LSC model. As can be seen, when the LSC CPU-MAX is regularly around 40uS, the receive error rate goes up from 2 to 10 errors per 16384 received packets.
At 10 errors per 16384 packets, the error rate is 0.06%. Can we determine if this is significant?
questions/ideas which have been mentioned when thinking about possible solutions:
reduce LSC processing (filter modules unnessary or unnessarily complicated) split LSC into two cores (again) delay the RFM receiver by one whole cycle (adds 60uS latency to control signal) replace LSC computer with faster hardware (being investigated by Rolf, Keith)