Reports until 00:04, Thursday 13 October 2011
H2 SUS
jameson.rollins@LIGO.ORG - posted 00:04, Thursday 13 October 2011 - last comment - 09:05, Thursday 13 October 2011(1554)
ITMY SUS ADC0 -> R0 wiring fixed (hopefully) in h2susitmy

I found what appeared to be some miswiring of a couple of channels from ADC0 to the R0 OSEM inputs to the ITMY QUAD_MASTER block in the h2susitmy model.  I found:

ADC0_18 -> R0_OSEM_F1
ADC0_19 -> R0_OSEM_F2
ADC0_20 -> R0_OSEM_F3
ADC0_22 -> R0_OSEM_LF
ADC0_23 -> R0_OSEM_RT
ADC0_21 -> R0_OSEM_SD

However, according to D1001725-v7 the wiring should be:

ADC0_20 -> R0_OSEM_F1
ADC0_21 -> R0_OSEM_F2
ADC0_22 -> R0_OSEM_F3
ADC0_18 -> R0_OSEM_LF
ADC0_19 -> R0_OSEM_RT
ADC0_23 -> R0_OSEM_SD

I didn't find anything in the aLOG or svn log to indicate that the wiring should be any different than what's in the wiring document linked above, so I went ahead and fixed the model and committed the change (r1230).

NOTE: I DID NOT REBUILD/INSTALL/RESTART THE MODEL.

Comments related to this report
jeffrey.garcia@LIGO.ORG - 09:05, Thursday 13 October 2011 (1555)
Link 

I had made some reordering changes to the "h2susitmy.mdl" to fix the older (committed) version according to the new D1001725-v7 document.  The changes I made were the same as mentioned above, but I did not commit the changes to the SVN because the Simulink diagram added a vertical line across the wiring coming from the ADC selector to the ADC inputs after I made the changes.  I wanted to confirm changes and resolve this issue before compiling/rebuilding/reinstalling.  A back-up of the earlier model before I made changes is in: '/ligo/svncommon/SusSVN/sus/trunk/QUAD/H2/ITMY/h2susitmy_111012_before_jeffg_changes.mdl'