It was found that the sus monitoring systems did not have channel 31 on ADC0 reserved for timing/duotone inputs. After some discussion it was determined that all IO chassis should have the same timing input signals, including all monitoring systems.
The SUS ETM (D1001725-v8) and BS/ITM/FM (D1002741-v4) wiring diagrams were updated to accommodate these signals. This also required updates to the h2susauxb478 and h2susauxb6 models, which were corrected and committed. However, while working on h2susauxb478 I found that there were some discrepancies in the input channel mappings. The wiring seems to be missing mappings for the following channels:
BS Left Slow I (rms)
BS Left Fast I
BS Left Volt Mon
BS Side Slow I (rms)
BS Side Fast I
BS Side Volt Mon
The model that was committed is therefore incomplete, and will need to be updated once the wiring diagram has been fixed. NOTICE: neither model was rebuilt or installed.
It turns out that the missing BS monitor channels were actually there, just mapped back up into ADC0. I have corrected the h2susauxb478 model with all channels, and recommitted.
NOTE: This model is still not rebuit or installed.