Version 3 (svn tag 97) FPGA code was loaded into all timing comparator/frequency counters. This addresses:

• The frequency readout was always one short with version 1 or 2 (initialization error).
• Frequency channels 3 and 4 did not have their termination enabled (horrible copy/paste error).
• Frequencies are now reliably measured up to 500 MHz (added prescalers).
• Up to 2 sec of unnecessary delay was removed from the transfer to TwinCAT/EPICS (adjusted timing of readout).
• So far, frequency readbacks have been stable and reliable (new counter logic).

There can still be a problem with crosstalk between channels, especially at frequencies above 200 MHz and signals stronger than 0 dBm. This has only been seen in open channels with no input. Channels with an RF input signal don't seem to suffer from it.

The CER and EX units were swapped with units which had a proper heatsink installed for the 5 V regulator. The following units were modified: