SUS ADC move, ETM to AUX

Richard, Jim, Stuart, Jeff, Dave:

The second ADC in the h1susex, h1susey IO Chassis were removed and inserted as a fith ADC in the h1susauxex, h1susauxey chassis. The IOP models h1iopsusex and h1iopsusey were modified to remove ADC1. This did not affect the SWWD code, it only reads ADC0 channels. The IOP models h1iopsusauxex and h1iopsusauxey were modifed to add ADC4. These models were started when the front ends were powered back up after the hardware swap.

PEM Mainsmon DAQ rate increase [WP5123]

Robert, Dave:

I increased the DAQ data rate for the PEM MAINSMON channels, including the quadrature sum, from 256Hz to 1024Hz as approved by Peter in DCC document T1400768. I discovered that the ODC part in the model did not differentiate between end stations, resulting in duplicate channels in the DAQ ini files. I renamed these parts ODC_X and ODC_Y to remove the duplication. The 60Hz mains AC voltage now looks like a clean sine wave in the DAQ (please see attached image). This closes WP5123.

Suspensions recalibration of 18bit-DACs

Jeff, Jim, Dave:

Jeff restarted the SUS QUAD IOP models to perform a recalibration of the 18bit-DAC cards. He noted that some restarts completed too rapidly for the calibration to have been performed successfully (should be 5 seconds per DAC card). This was an intermittent problem, we should investigate on the DTS.