Displaying report 1-1 of 1.
Reports until 17:02, Saturday 04 April 2015
H1 ISC
sheila.dwyer@LIGO.ORG - posted 17:02, Saturday 04 April 2015 - last comment - 16:05, Monday 06 April 2015(17689)
DIFF PLL board glitches, probably will prevent IFO locking

Koji, Sheila

Koji and I searched around for the source of the periodic (every 4 second) glitch in DARM control when locked on ALS figure attached to 17684.  The problem seems to be the DIFF PLL board, we were able to see the glitches in the PLL control signal when it was locked to a marconi instead of the DIFF beatnote.  We locked the DIFF beatnote using the COMM PLL board, saw no glitches, and also swapped the ADC cables to make sure the DIFF ADC channels were fine.  I don't know where the spare is, so we are elaving the chassis in the rack for now, but the board needs to be swapped before we can get back to locking the full IFO reliably. 

Just too be clear, it seems likely these are a different class of glitches from those described in 17576 and linked alogs

Comments related to this report
daniel.sigg@LIGO.ORG - 12:54, Monday 06 April 2015 (17697)

We made some additional tests this morning but couldn't see anything obviously wrong. There is a fair amount of RF interference between the 3 VCOs which depending on the exact frequencies looks bad. 

Some additional observations:

  • The DIFF VCO readback was coming from the first FDD rather than the second. So what we recorded as the DIFF VCO frequency was actually 10*(f_DIFFVCO-71MHz). Fixed now.
  • Most of the COMM and DIFF interference seems to be originating in the PFD chassis. In particular, establishing a short between the chassis and the LO connector greatly reduced the amplitude of the interference signals. We probably should add capacitors to avoid ground loops.
  • The PLLs are running at ~100kHz bandwidth. This is not really necessary. The control signal is used as an error signal in DARM and CARM with much lower bandwidth. On the other hand the interference signals are out-of-loop and mostly injected at the input. So, they get multiplied by the open-loop PLL gain until they wander in band.
evan.hall@LIGO.ORG - 16:05, Monday 06 April 2015 (17707)CDS

Eventually we figured out that with DIFF and COMM unlocked, these 4-second glitches were showing up in the Y end green control signal, and not in X.

So we drove down to EY and found that the EY ESD driver was tripped. We could hear that it was trying to reset itself every 4 seconds or so. Untripping the driver made the glitches go away.

It is unclear whether this was actually kicking the test mass, or coupling into the green readout some other way.

Displaying report 1-1 of 1.