Peter, Calum, Ben, Rich Took transfer functions (1Hz to 10kHz, 255 points in to the DAC Drive Input on the front panel of the ESD driver, out of the respective SHV connector going to the ETM) of all the quadrant paths of the newly installed LN Driver. The results are stored in: /ligo/svncommon/CalSVN/aligocalibration/trunk/Runs/PreER7/H1/Measurements/ElectronicsMeasurements/ under the following file suffixes UR -> TFSR785_22-05-2015_102054.txt LR -> TFSR785_22-05-2015_102804.txt UL -> TFSR785_22-05-2015_103546.txt LL -> TFSR785_22-05-2015_105053.txt Everything looks good as compared to the Spice model. Also, we measured the output noise of each channel at 20Hz with and without DC bias. Results are all consistent with the design (<40nV/rtHz at 20Hz and above) and Spice model. 0V bias/-7.4V bias UR -> 21nV/rtHz/32nV/rtHz LR -> 22nV/rtHz/30nV/rtHz UL -> 23nV/rtHz/37nV/rtHz LL -> 28nV/rtHz/37nV/rtHz Analyzer Noise Floor 10nV/rtHz @ 20Hz Typical output noise at higher frequencies is: 20nV/rtHz @ 50Hz, 22nV/rtHz @ 100Hz, 20nV/rtHz @ 150Hz Noticed that there is still a discrepancy in the DAC monitors for the user model vs. the IOP. Richard has the details and Jeff will likely follow up next week. Once Richard sorts out the somewhat touchy vacuum interlock (he's working on that now and knows the problem), the entire system is now functional and ready for use.
Plot attached.
For the purposes of figuring out the appropriate compensation for DARM, I also plotted a simple model which just contains the effect of the LPF stage (2 poles at 2.2 Hz, 2 zeros at 50 Hz) and the PI summing node (pole at 152 Hz, zero at 3.2 kHz). The effect of the summing node is not yet digitally compensated, so that could explain the loss of phase that we saw in the DARM OLTF last night (about 50° at 200 Hz).