Sheila's alog from last night (20055) indicated that they were seeing locklosses during the transition to the ETMY ESD again.   After some investigation, I believe that I have found and solved the problem, so hopefully we won't see those anymore.

The problem was that the SUS-ETMY_L3_LOCK_L gain was being set to zero in the COIL_DRIVERS state (one state before the LOWNOISE_ESD_ETMY state) while there was a large ramp time in the filter bank (input was off at this time, although output was on).  There is no timer or wait time after this.  In the next state (LOWNOISE_ESD_ETMY), the ramp time is explicitly set to zero, and then the gain is set to zero.  However, since the gain had already been set to zero with a long ramp time, and EPICS doesn't acknowledge a write command if the value isn't going to change, the gain was still slowly ramping to zero over 10 seconds.  The LOWNOISE_ESD_ETMY state assumed that the gain had been immediately set to zero, so it turns on the input immediately.  This is sending large signals out, which are also getting sent up the chain to the L2 and L1 stages. 

To solve this, in the COIL_DRIVERS state where the gain is first set to zero, I first set the ramp time to zero (the ramp time is already explicitly set to seconds immediately before the big ETMX->ETMY transition at the end of the LOWNOISE_ESD_ETMY state).  The input is off at this time, so we should not see a difference at this state.  The DOWN state actually turns off the input and turns off the gain, so I'm not sure why the gain is ever non-zero before the LOWNOISE_ESD_ETMY state.  Even if I don't find where the gain is set to a non-zero value between the DOWN state and the LOWNOISE_ESD_ETMY state, this problem is now (hopefully) solved.