We consolodated those system which will remain in the MSR into the far rack (which is the only rack which will remain in the MSR). This required powering down the timing systems, which stopped the H2 front ends, the H2 DAQ and the test stands in the staging building. We also rerouted the GC networking.

The timing master was upgraded at the same time. The DC power to the IO Chassis at EY was reconfigured such that one 24V supply feeds SUS and SEI, and the second 24V supply feeds PEM and TCS.

h2dc0 was power cycled, as well as all front ends and their IO Chassis as part of the recovery. All frontends were burt restored to 11:00am, except susitmy which was restored to its safe.snap file.

Yesterday the LDAS fiber optics panel, the Q logic switch and the tape robot cables were moved from the MSR to the computer users room.