jeffrey.kissel@LIGO.ORG - posted 13:30, Thursday 27 August 2015 - last comment - 17:28, Monday 31 August 2015(20958)
IFO Taken down to take LSC and END SUS DAC DuoTone Timing Checks
J. Kissel, K. Kawabe, S. Karki We've broken observation mode such that we can enable the DAC DuoTone timing readbacks on the front ends that are responsible for DARM control, i.e. h1lsc0, h1susex, and h1susey. We needed to take the IFO down for this because the last channel on the first DAC cards for the end station SUS are used for top-mass OSEMs for damping the suspensions. If the damping loops get a two sign waves at 960 and 961 [Hz] instead of the requested control signal for one of the OSEMs, then we get bad news. Here are the times when the DAC DuoTone switches were ON for the following front ends: h1susex and h1susey --- 19:04 to 20:04 UTC (12:04 to 13:04 PDT) h1lsc0 --- 19:16 to 20:06 UTC (12:16 to 13:04 PDT) Though all relevant channels (ADC_0_30, ADC_0_31, DAC_0_15) are free on the h1lsc0 front end, we elected to turn the DAC DuoTone off, so that we aren't in danger of an oscillitory analog voltage being sent around the IO chassis that's used to measure the OMC DCPDs. Data and analysis to come. The IFO will be staying down for a few hours, while we finish up some electronics chain characterization of the OMC DCPD analog electronics (along with some other parasitic commissioning measurements).
I showed Sudarshan which signal to look at and how to analyze them. He will make an awesome drawing of how things are connected up in this alog.
The first and second attachment shows the duotone timing of the signals pulled from the IOP channels (all 64kHz). The results are summarized in the following table.
Measurement time (UTC)
As per yesterday's alog, duotone is about 7.3usec delayed behind LSC ADC, and actually this turned out to be the case for all ADCs.
According to Zuzsa Marka, duotone was "delayed a bit above 6 microseconds compared to the GPS 1pps" (report pending), so probably this means that the ADC timing (i.e. time stamp of ADC) is decent.
Duotone round trip delay for all IOPs except IOP-LSC0 is about 61us or about 4 64k-clock cycles. For LSC0, this was about 5 64k-clock cycles.
I don't know where the difference comes from. This is totally dependent on how the 64kHz ADC input is taken, routed to 64kHz DAC when "DT DAC" bypass switch is in "ON" position (third attachment), and finally output by DAC, but I don't think there should be difference between LSC and everybody else. At least LSC DAC timing doesn't come into the DARM timing.
The next table is for 16kHz pcal channels on the frame. The measurement results as well as the channel names are shown in the last attachment.
(raw, raw-decimation)
ADC0 Ch30 (direct in without AI and AA)
(raw, raw-decimation)
(124.92, 68.99)
377.72
(raw, raw-decimation)
(124.89, 68.96)
377.07
For Ch31 and Ch30, the routing is done bypassing the user model, the signals are merely imported into the user model and decimated.
Sudarshan found the 4x decimation filter delay to be 19.34deg or 55.93us at 960.5Hz, and "raw-decimation" number is obtained by just subtracting this from the raw number. This is consistent with the 64kHz result, so from now on we can look at 16kHz signals as far as pcal is concerned.
I don't know anything about AA and AI, so I'll leave the analysis to Sudarshan.
Relevant scripts and dtt templates are in /ligo/home/keita.kawabe/Cal/Duotone.
Keita's alog explained the timing on Duotone to ADC and DAC to ADC loop as well. Additionally in pcal, channel 28 is routed through the analog AI and AA chasis. The details about how the channels are connected can be found in the attached schematics.
From the schematics we can see there are three (3) 4X decimation filters (two downsampling and one upsampling) in this particular chain (Channel 28). This amounts 3*55.93 us = 167.79 us of delay (each of these filter produce phase delay of 19.34deg or 55.93us at 960.5Hz). The analog AA and AI chassis produce phase delay of 13.76 degrees which amounts to about 39.82 us at 960.5 Hz from each chassis totaling in 79.64 us of time delay.
Total Delay = 3*55.93+2*39.82 =247.73 us.
Column 3 contains the measured (raw) time delay and "raw- total delay".
Column 4 contains the roundtrip time (raw-timedelay-7 us) = ~ 122 us (8-64 KHz cycle).
ADC0 Ch28 (with AI and AA)
(raw, raw-(3*decimation+2*analog AA/AI))
(377.72, 130.29)
ADC Ch28 (with AI and AA)
(raw, raw-(3*decimation+2*analog AA/AI))
(377.07, 129.64)
(raw, raw-decimation)
ADC0 Ch30 (direct in without AI and AA)
(raw, raw-decimation)
(124.92, 68.99)
377.72
(raw, raw-decimation)
(124.89, 68.96)
377.07