J. Kissel, K. Kawabe

Similar to what is shown and briefly mentioned in LLO aLOG 18406, I've done a comprehensive transfer function study between the DAC and ADC Duotone timing signals from the following IO chassis:
h1lsc0 (which houses the ADC for the OMC DCPDs),
h1susex & h1susey (which house the DACs for the ETM QUADs)
h1iscex & h1iscey (which house the ADC for the PCAL RXPDs)
h1oaf0 (which receives the DARM_ERR and DARM_CTRL channels from the OMC model over IPC)
Recall that these Duotone signals are merely *checks* on the system that is actually providing the time signals for the DAC / ADC cards, which is the 1 PPS signal from the local timing fanout in the building (which in in turn receives its 1 PPS from the timing master in the corner station which is GPS synchronized). The results indicate that -- although there is a few tens of micro-second offset between all of these front-ends, they appear to not *differ* by more than a few hundred nano-seconds, and typical in the tens of nano seconds. This is consistent with what Shivaraj found when making the comparison between his l1iscex and l1iscex against l1oaf0. Recall that our requirement is that the timing uncertainty is no greater than 25 [us], so at least the DuoTone signals between each IO chassis fall in well-below this. What we would need to do to confirm that the actual front end timing is to then compare this DuoTone against the "digital world" 1 PPS, as Keita has done for the ADC and DAC DuoTone signals for all of the above mentioned chassis in LHO aLOG 20962. His aLOG also indicates a ~100 [ns] difference between chassis, on top of the ~7 [us] offset.

So far, so good in timing land.

Details:
---------
For all measurements, I used h1lsc0 ADC and DAC duotone singals as the reference (TF denominator), and the others as the response (TF numerator). Below are the results for the phase relationship between each at 960 [Hz] (the results are the same within the precision stated for the 961 [Hz] line):
          xxxx ADC      xxxx DAC      xxxx ADC     xxxx DAC
          --------      --------      --------     --------
          LSC0 ADC      LSC0 ADC      LSC0 DAC     LSC0 DAC

h1lsc0       n/a         -26.42        +26.42         n/a
h1susex    +5.14         -21.27        +26.45       +5.14
h1susey    +5.13         -21.28        +26.44       +5.13
h1iscex   +0.008         -21.29        +26.45       +5.13
h1iscey   +0.028         -21.27        +26.47       +5.14
h1oaf0    -0.013         -21.34        +26.43       +5.07

which we can turn in to an equivalent delay (or advance) between the two front end timing signals, with 1e6 * (pi/180) * phase_deg * / (2*pi*961 [Hz])
          xxxx ADC      xxxx DAC      xxxx ADC     xxxx DAC
          --------      --------      --------     --------
          LSC0 ADC      LSC0 ADC      LSC0 DAC     LSC0 DAC
            [us]          [us]         [us]          [us]
h1lsc0       n/a         -76.4         76.4          n/a
h1susex     14.9         -61.5         76.5          14.9
h1susey     14.8         -61.6         76.5          14.8
h1iscex     0.023        -61.6         76.5          14.8
h1iscey     0.081        -61.5         76.6          14.9
h1oaf0     -0.038        -61.7         76.5          14.7

Templates live in 
/ligo/svncommon/CalSVN/aligocalibration/trunk/Runs/ER8/H1/Measurements/Timing/
2015-08-27_H1LSC0_to_CALCS_DuoTone_TFs.xml
2015-08-27_H1LSC0_to_ISCEND_DuoTone_TFs.xml
2015-08-27_H1LSC0_to_SUSEND_DuoTone_TFs.xml
of which I attach an example.