ECR: https://dcc.ligo.org/LIGO-E1500373

userapps/cal/common/models/PCAL_MASTER.mdl

1. Changed it such that IN1 instead of OUT duotone channels are recorded on frame so there's no way timing information is compromised by user error.
2. FPGA duotone IN1 (not output) is in science frames at 16k. There are two end stations, so two new 16k channel in science frame per IFO.

userapps/omc/h1/models/omc.mdl

1. FPGA duotone (ADC0 CH31) is sent to OMC common block.

userapps/omc/common/models/omc.mdl

1. FPGA duotone signal is sent to cdsFilt in the omc block, and IN1 is recorded as OMC-FPGA_DTONE_IN1_DQ in science frame at 16k. The name was chosen so that the pcal and omc signals are consistent.

h1calex, h1caley and h1omc were all successfully built but not installed. These will be installed on next Tuesday.