Displaying report 1-1 of 1.
Reports until 12:42, Monday 05 March 2012
H2 SEI
christopher.kucharczyk@LIGO.ORG - posted 12:42, Monday 05 March 2012 (2357)
Summary of changes to ISI and HPI models
Summary of changes made:

Last revision prior to changes is revision 1911. To reset Hanford userapps to the old ISI systems, please revert the HPI and ISI common and H2 folders to revision 1911 and re-make h2isiitmy and etmy, h2hpiitmy and etmy, . Revision 1912-1913 are changes to the master model including the new control. Revision 1913 and 1914 are medm screen revision, 1915 is controls on the master model. Revision 1916 includes the changes to h2isiitmy.

HEPI Changes:
On h2hpiitmy.mdl, I added in three ADCs: ADC0, ADC1, ADC2. These were all terminated. Prior to that, only ADC3 (card num = 3) was in the model. I also changed the bus outputs from the ADC selector, since they were previously connected with arrows copy-pasted from ADC0.
No changes were made to the hepi template.

ISI Changes:
For h2isiitmy, DAC_0 (card_num=0) and DAC_1 (card_num=1) were placed in ISI model - DAC_0 connected to ground entirely since it is shared with HPI. Previously, 

Lots of controls changes were made: feed forward and sensor correction from 0->1 and 1->2. These new controls all had the outputs from their output filters grounded so that no additional signal would be added to the model until 

Compiles - The models were compiled at various points to test out an ADC problem - the channels at the input to the ADC did not have the same value as the channels at the input to the HEPI model. At one point, the HEPI model was compiled at 4k to test.

In terms of what might have caused the motion craziness, the changes I made were either internal - prior to the overall output watchdog - or external - adding or changing ADC and DAC connections. The watchdog should have still prevented any model changes from driving the platform differently. The changes that might have caused problems with I/O inter-connect problems would have been 
1) adding the HEPI DAC to the ISI model, 
2) adding the three ADCs (0, 1, and 2) to the HEPI model, 
3) changing the connections from the HEPI ADC3 to the hepitemplate block, or 
4) recompiling the hepi model at 4k rather than 2k rate to test out the IOP problem we were having.

I'll edit/comment on this as more comes to mind, feel free to e-mail me additional questions or comments.
Displaying report 1-1 of 1.