Hannah Fair, Stefan Ballmer

Some of the ASC and LSC ODC bits that were not in the master bit mask were occasionally triggering mid-lock, without any obvious data degradation.
I updated the thresholds listed below. Since the IFO is currently not locked, the SDF is currently very red.

THE SDF PROBABLY NEEDS TO BE UPDATED WITH THESE THRESHOLDS.

# ASC
ezca['ASC-ODC_REFL_A_DC_LT_TH'] = -150
ezca['ASC-ODC_REFL_B_DC_LT_TH'] = -150
ezca['ASC-ODC_REFL_A_DC_GT_TH'] = -1000
ezca['ASC-ODC_REFL_B_DC_GT_TH'] = -1000
ezca['ASC-ODC_REFLA_DC_PIT_LT_TH'] = 0.3
ezca['ASC-ODC_REFLA_DC_YAW_LT_TH'] = 0.3
ezca['ASC-ODC_REFLB_DC_PIT_LT_TH'] = 0.3
ezca['ASC-ODC_REFLB_DC_YAW_LT_TH'] = 0.3
ezca['ASC-ODC_CHARD_PIT_LT_TH'] = 1000
ezca['ASC-ODC_CHARD_YAW_LT_TH'] = 1000
ezca['ASC-ODC_DHARD_PIT_LT_TH'] = 3500
ezca['ASC-ODC_DHARD_YAW_LT_TH'] = 3500
ezca['ASC-ODC_PRC1_PIT_LT_TH'] = 2000
ezca['ASC-ODC_PRC1_YAW_LT_TH'] = 2000
# LSC
ezca['LSC-ODC_MICHCTRL_LT_EQ_TH'] =  300000
ezca['LSC-ODC_MICHCTRL_GT_EQ_TH'] = -300000

Old values:
ASC-ODC_REFL_A_DC_LT_TH -150.0
ASC-ODC_REFL_B_DC_LT_TH -300.0
ASC-ODC_REFL_A_DC_GT_TH -900.0
ASC-ODC_REFL_B_DC_GT_TH -750.0
ASC-ODC_REFLA_DC_PIT_LT_TH 0.2
ASC-ODC_REFLA_DC_YAW_LT_TH 0.2
ASC-ODC_REFLB_DC_PIT_LT_TH 0.15
ASC-ODC_REFLB_DC_YAW_LT_TH 0.15
ASC-ODC_CHARD_PIT_LT_TH 750.0
ASC-ODC_CHARD_YAW_LT_TH 750.0
ASC-ODC_DHARD_PIT_LT_TH 2500.0
ASC-ODC_DHARD_YAW_LT_TH 2500.0
ASC-ODC_PRC1_PIT_LT_TH 1500.0
ASC-ODC_PRC1_YAW_LT_TH 1500.0
LSC-ODC_MICHCTRL_LT_EQ_TH 150000.0
LSC-ODC_MICHCTRL_GT_EQ_TH -150000.0