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Reports until 18:40, Thursday 18 February 2016
H1 ISC (ISC)
jenne.driggers@LIGO.ORG - posted 18:40, Thursday 18 February 2016 - last comment - 09:54, Friday 19 February 2016(25630)
ASC progress: closing loops around better phasing

[Jenne, Sheila, Den, Hang, Keita]

We started the day by phasing the REFL WFS, both A and B, in both 9 and 45.  In particular, we knew that the 45 MHz phasing was weird.  Hang will post a reply with our detailed procedure.

We also reverted the AS 36 A&B demod phases to the values that Sheila had found on Sept 1 (alog 21083). 

With this new phasing, we started trying to close WFS loops. 

We captured the state of the ASC in a snapshot (saved in the same folder as the SDF's snap files), and then reverted everything to the down.snap file so that noise hunting work can happen tonight.

All of today's work was done in DRMI-only, since the wind was much too high to hold the arms with ALS.  So, we'll have to re-visit these phasings, but hopefully they'll only be small tweaks in full lock.

We have not yet closed the loop on the new AS 90 centering loops, since we got a bit confused earlier in the day when (it turns out) there wasn't any light on the AS WFS.  Keita has set gains and phases to match the current DC centering loop, so we should be able to just change the input matrix elements (same values) over to the AS 90 column.

Overall a good day, but we need to keep pushing forward.

Comments related to this report
hang.yu@LIGO.ORG - 09:54, Friday 19 February 2016 (25637)ISC

The detailed procedrue we used to phase the REFL WFS' is summerized below:

 

### determining the relative phase of 4 quardrants using the length signal ### 

Drive IMC_MCL_EXC with ~1000 cts at 4 Hz.

Turn on 4 Hz bandpass filters in I1-I4, Q1-Q4 filter banks

Phase s.t. the signal in each quardrant apears in I phase. 

Looking at 4 I channels together to make sure no they are in phase and no sign flip.

Turn off MCL drive.

 

### checking the phase for alignment signals ###

Turn on resG filters in MICH, PRCL, SRCL.

Drive PR2 M3 by dithering pit or yaw, 1 at a time

Confirm I1, I2 in phase and I3, I4 opposite phase for pit; I1, I4 in phase and I2, I4 opposite phase for yaw.

Turn off PR2 drive; turn off resG in length loops; turn off bp filters in segments.

Done.

 

### step size for phase adjusting ###

1 deg for 9 MHz, 5 deg for 45 MHz

#########################################

Using the way above, the new phases for the REFL WFS are (in [deg])

Phase for REFL WFS
  old new
A_9 -97.5 -74.0
  -88.0 -73.0
  -58.0 -74.0
  -65.0 -69.0
A_45 -165.0 -115.0
  -175.0 -120.0
  -45.0 -95.0
  -50.0 -105.0
B_9 -83.0 -83.0
  -85.0 -87.0
  -85.0 -84.0
  -79.0 -81.0
B_45 -245.0 0.0
  -235.0 0.0
  245.0 10.0
  250.0 0.0
denis.martynov@LIGO.ORG - 04:46, Friday 19 February 2016 (25633)
Kiwamu, Evan, Den

We have continued ASC work in full lock. We concentrated on AS 36 signals since they are the most problematic. In the past we had to control SRM and BS using a combination of A and B, I and Q signals and switch them at different states. Tonight we have phased AS_36 A  WFS in full lock and used only Q -> BS and I -> SRM signals during the whole lock acquisition sequence. This WFS is phased such that BS is in Q and SRM signal is equally split between I and Q. We did the similar phasing with AS_36 B WFS, but this diode has an offset and does not maximize the power. We have also noticed that phase of this WFS changes by 45 degrees when we increase the power. For these reasons we do not use it during the lock acquisition.

We also noticed that when interferometer reaches 0 CARM offset, power recycling gain is around 33 and PRC WFS switch sign. We have updated the reference for ITMY camera servo in the initial alignment such that interferometer locks with high power recycling gain.

We have also witnessed several lock losses in the state when DARM WFS are engaged and DARM is switched to RF from ALS. There is a large peak at 9Hz in the DARM loop with saturates the ESD driver. We should look more carefully into this issue.
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