I injected into the 2nd loop board via PSL-ISS_TR (3rd looop filter) and SR560, and measured the transfer function from the readback of the analog input (H1:PSL-ISS_SECONDLOOP_PD_58_SUM_OUT, which is 32k channel) to the readback of the analog output ( H1:PSL-ISS_SECONDLOOP_SIGNAL_OUTPUT, which I think is in the 1st loop board) when the gain is set to 0, BOOST off, integrator off.

I was confused because of an additional 500Hz pole, but it seems like this was a questionable 500Hz digital pole in H1:PSL-ISS_SECONDLOOP_SIGNAL FM1. Anyway, in the attached, dots are as measured but after counter-compensating for the questionable 500Hz digital pole, and the lines are what is expected from D1300439 and S1400214.

The analog TF of the board itself should be something like zpk([1, 100, 8.46k, 10k], [0.1, 0.5, 500, 33.9k], 350). Yes there's 500Hz pole in analog. This is like one 0.1Hz pole up to 100Hz with some funny additional things (but don't forget SR560 with AC coupling and 10Hz pole, SR560 is used as a poor man's dewhitening to cut the DAC noise).

To make the 3rd loop design without 2nd loop somewhat easier, I made a simple zpk([0.1;0.5], [1;10; 50], 1) in FM9 of H1:PSL-ISS_TR called boardComp to get rid of p=[0.1, 0.5] and z=1. The potential problem of this is that the SR560 might rail. If this happens, we need something better.

Anyway, the starting point is to turn this filter on, then set the gain to whatever it was originally and divide it by 350, and measure the OLTF of the third loop without the second loop while the loop is open.