szymon.steplewski@LIGO.ORG - posted 15:50, Monday 14 May 2012 - last comment - 23:19, Monday 14 May 2012(2845)
Testing L2 OSEMs
Szymon Steplewski, Jeff Garcia, Mark Barton, Fred Raab This afternoon we tested the ITMY lower stages to check whether the OSEM actuators were working correctly. We found that upon exciting stage L2 the UL OSEM was not registering any change in the voltage monitor H2:SUS-ITMY_L2_VOLTMON_UL_MON, while the other three seemed to be responding to our excitation. The corresponding NOISEMON channels also indicated that the UL OSEM was acting differently from the other three. We decided to try injecting a 1 Hz sine wave excitation and looking at the time series of the VOLTMON and FASTIMON channels. Our test confirms that each OSEM is responding correctly to this monochromatic drive, except for the stage L2 UL OSEM. We will next diagnose whether this is a hardware or software related problem.
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Comments related to this report
The tests run this afternoon revealed a discrepancy in our coil out drive channels and the corresponding OSEM readout (pd's). At the L2 stage, an actuation from the "H2:SUS-ITMY_L2_TEST_L_EXC" in DTT should drive all four face OSEMs on the PUM, equally. The attached image on the initial post shows the response of the "H2:SUS-ITMY_L2_VOLTMON_*" channels when driving the "*_TEST_L_EXC" with a 1Hz sine wave (amp. = 100cts). There does appear to be some coherent response from the "*_UL" OSEM, but with not nearly as high an amplitude. The "*_VOLTMON_*" channels read out a picked-off signal from the SUS Satellite Amplifier box. The channels should provide the raw analog voltage (though through an ADC) to each OSEM coil drive channel. This discrepency is either due to hardware mapping in the Simulink models (which map ADC and DAC channels) to the wiring diagram or an OSEM malfunction.
The user model ("h2susitmy.mdl") and the IOP models each were outputing DAC signals to the appropriate DAC channels ("H2:FEC-28_DAC_OUTPUT_2_*" and "H2:FEC-30_DAC_OUTPUT_2_*") during these tests. But this is not a good test of the hardware signals - that merely affirms the model compiled correctly as labeled and is communicating with the IOP. The appropriate tests needed are analog voltages readouts in-line along the signal chain (UK satellite amps). A subsequent post will detail the results from further tests conducted later in the evening.