Completed the timing FPGA upgrades

Daniel, Ansel, Richard, Jim, Dave:

The remaining timing systems were upgraded to the "non-blinking" FPGA code. The units upgraded today were: master in MSR, two fanouts in CER, fanout in EY (EX was upgraded last week). All front end IO Chassis were power cycled for the upgrade.

Prior to the power down of the h1oaf0 chassis, the TCS chiller control cables were unplugged from the chillers (located on the Mech Room Mezzanine). These were reconnected when the reboots were completed.

Prior to the power up of the SEI IO Chassis, the AI chassis were powered down following the procedure in DCC-T1600332. Similarly, the AI chassis for ISC and PSL were powered down prior to IO Chassis power up. The AI chassis were restored to power when all front end code was running.

All front ends in MSR, EX, EY, MX and MY were power cycled. IRIG-B in MSR was power cycled, IRIG-B at EX, EY were not.

Removal of Binary IO Cards from SEI H16 and H23

Richard, Fil, Jim:

unused BIO cards were removed from the IO Chassis for h1seih16 and h1seih23

Addition of Binary IO Card into PSL

Richard, Jim, Dave:

A new BIO card was added to the IO Chassis for h1psl0. This is the first BIO card for this system and will be used for next week's new ISS tests.

New SUS QUAD code

Jeff, Jim, Dave:

Jeff completed his new QUAD code install on h1susitmx, h1susitmy, h1susetmx, h1susetmy. DAQ restart was needed to add slow channels.