J. Kissel In short: The ETM ESD bias signs have now been flipped. After whining about it since ER9, I've commissioned why the bias sign flipping had caused the ALS DIFF control to go unstable (and subsequently DARM once we get onto ETMY): controlling the loop gain sign beyond the ESD linearization just doesn't work. As such, I've restored all settings for both test masses to their successful settings back in April -- namely that from LHO aLOG 26826. As such, we've returned to the aesthetically displeasing but functional method of controlling the DARM loop sign in the DRIVEALIGN matrix. We still have yet to assess the impact on PI damping. ---------------------- Explicit details for the next time this becomes confusing: ETMX (1) Changed H1:SUS-ETMX_L3_LOCK_INBIAS from -9.5 [V] to +9.5 [V] (2) Changed H1:SUS-ETMX_L3_DRIVEALIGN_L2L_GAIN from +1.0 to -1.0 H1:SUS-ETMX_L3_DRIVEALIGN_L2P_GAIN from +0.021 to -0.021 H1:SUS-ETMX_L3_DRIVEALIGN_L2Y_GAIN from +0.007 to -0.007 (3) Changed H1:SUS-ETMX_L3_ESDOUTF_LIN_FORCE_COEFF from -124518.4 to +124518.4 (4) Made sure all H1:SUS-ETMX_L3_ESDOUTF_??_GAIN fields are +1 always, all the time, as before. (No changes need to the calibration model since we don't use ETMX in our lowest noise state.) ETMY (5) Changed H1:SUS-ETMY_L3_LOCK_INBIAS from +9.5 [V] to -9.5 [V] (6) Changed H1:SUS-ETMY_L3_DRIVEALIGN_L2L_GAIN from +30.0 [V] to -30.0 [V] (7) Changed H1:SUS-ETMY_L3_ESDOUTF_LIN_FORCE_COEFF from +124518.4 to -124518.4 (even though ETMY doesn't use linearization). (8) Made sure all H1:SUS-ETMX_L3_ESDOUTF_??_GAIN fields are +1 always, all the time, as before. (9) Changed H1:CAL-CS_DARM_FE_ETMY_L3_DRIVEALIGN_L2L_GAIN from +30 to -30 (10) Changed H1:CAL-CS_DARM_FE_ETMY_L3_ESDOUTF_UL_GAIN from -1 to +1, where it should remain always, all the time, as before. (11) Changed H1:CAL-CS_DARM_FE_ETMY_L3_ESDOUTF_LIN_FORCE_COEFF from +124518.4 to -124518.4 (even though ETMY doesn't use linearization). I've also redone (essentially reverted) the DOWN state in the ISC_LOCK guardian with respect to the ETM ESD settings, such that steps 2-3, and 6-11 are done automatically if a user does steps 1 and 5. Once we figure out the impact on PI damping, we'll code these up in the DOWN state of the ISC_LOCK guardian as well. Finally, I've accepted these changes into the H1SUSETMX down.snap (to which its safe.snap is a soft link) H1SUSETMY down.snap (to which its safe.snap is a soft link) H1CALCS safe.snap and OBSERVE.snap. SDF systems.
I have flipped PI ETM damping gain signs and confirmed successful damping many many times now. I've added a bias flip check to the SUS_PI guardian under the PI_DAMPING state; this will choose sign of gain based on sign of ETM bias.