Reports until 22:13, Thursday 15 September 2016
H1 ISC
terra.hardwick@LIGO.ORG - posted 22:13, Thursday 15 September 2016 - last comment - 11:59, Friday 16 September 2016(29747)
PI 3 hour 50W lock status

Matt, Terra

Status of PI after TCS work and ring heater change transient (for at least the first three hours of 50 W lock):

  1. Successfully damping all modes (with some caveats; see #4,5.)
  2. Actively damping ITMX 15520, ITMY 14980 and 15515, ETMX 15541 and 15008, ETMY 15542, 15009, 18041 and 18059 Hz. Of these, the 18kHz and 15kHz only ring up during the transient. 
  3. All modes are now getting damped using the PLL. One motivation for this is avoiding saturations. I'm fairly certain that the mysterious sign flips and illogical behavior when increasing gain in the past have been due to something saturating along the loop, usually resulting in ringing up the mode. 
  4. 15009 Hz (MODE 26) is still a bit confusing: it rings up twice during the transient period and appears to require a sign flip to damp each time. I'm not yet convinced this isn't just a byproduct of the transient though (we flip a gain sign and see a slow downturn on the same timescale as the transient passing, attributing the turn around to the wrong reason?). 
  5. After ~2 hours, 15541/2 Hz (MODE 17/25) ring up. While we have the actuation strength to damp these, these modes are ~.5 Hz apart, so the PLL is having trouble staying on the right one and I had to do lots of actively jumping back and forth between controls. We are going to try sending both drive signals to both optics, etc. 

3 hours into the lock and all PI's are stable. Leaving PI control with Matt for the night. 

Comments related to this report
matthew.evans@LIGO.ORG - 03:43, Friday 16 September 2016 (29752)
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Another 3 hour lock and similar PI story.

  • Mode 2 (15520 Hz on IX) is our poster child for PI damping.  It is clearly unstable without a damping loop, but the damper keeps it down nicely.
  • Mode 26 (15009 Hz on EY) has a sign flip near the start of the lock.  The PLL_PRE_OFFSET is currently set to try to avoid problems (keeps the feed back off until it is needed, which means that the sign can be wrong and the damper won't drive up the mode).
  • Modes 17 and 25 (15541.1 and 15541.9 Hz on EX and EY) were problematic (see plots).  They are very close in frequency, and they ring up at the same time, so the PLLs both have the same input and tend to both lock on the same mode (most often 15541.1).  I tried to address this by moving MODE17_PLL_SET_FREQ to 743 (which aliases/images to 15543) and clearing the MODE17 PLL integrator (FREQ_FILT2) when both PLLs locked on the same mode.  This seemed to work, so finally I changed the SUS_PI guardian to make it not enable the MODE17 integrator.  After this the modes did not ring up, but I don't think the relationship was causal.  We should look at making linear combinations of TRX and TRY to separate these modes in the sensing.  (I think Carl had done this with some success in the past.)
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terra.hardwick@LIGO.ORG - 11:59, Friday 16 September 2016 (29762)
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These modes shift very little in frequency during a lock stretch (see attached). I've tightened up the individual band passes quite a bit (~1 Hz) to see if that helps next lock. Still need to check lock to lock variation.

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