stefan.ballmer@LIGO.ORG - posted 01:05, Sunday 23 October 2016 - last comment - 23:24, Sunday 23 October 2016(30759)
SRC1 loop closed at 25W using AS36_A_I
Plot 1 shows the DC signals of all 4 I segments of ASA36. Note that seg 3 is ~2.5 times larger than the others.
Plot 2 shows the updated AS_A_RF36_I matrix - the gains for seg 3 have been dropped to -0.4 from -1.
Plot 3 shows the resulting error signal - it now cresses zero where the buildups and couplings for SRCL are good.
Closed the SRC1 PIT and YAW loops with a gain of 10, and input matrix element of 1. I will leave this setting for the night - although it is not in guardian yet.
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I accepted the funny matrix in SDF, and added this in the SRM ASC high power state. The loops should only come on for input powers less than 35 Watts. Nutsinee and I tested it once.