The PM1 suspension started swinging longer than usual and exceeded its RMS trip levels for 20 minutes continuous at 11:44 PDT this morning. This caused an IOP DACKILL on all three LIGO-DACs.

I was able to reset and bypass PM1 and restore the SUS DAC drives at 11:57.

Currently HAM1 SWWD has PM1 permanently bypassed so this cannot happen again.

J. Freed, J. Kissel

We worried for the production, already class-A clean, SPI's single-element PD (SPD) assembly (D2600001) that the unused GAP5000 pins of the dual-purpose D1700116 ceramic circuit board may have shorts from FFD-200 SPD case to its anode and cathode if the case of the PD was not insulated from those GAP5000 pins -- as was found possible in the dirty test setup (see list item 2. in LHO:89247).

This morning, we opened up the cleaned assemblies (still serialized under the drawing for the cable, D2400341),
    - S2500514 :: HAM3 ISIK MEAS A and MEAS B
         --Pins 5-9 -> PD Box S2400197 -> DCPD 001
         --Pins 4-8 -> PD Box S2400198 -> DCPD 002
    - S2500515 :: HAM3 ISIK FBR PWR REF and FBR PWR MEAS
         --Pins 5-9 -> PD Box S2401094 -> DCPD 004
         --Pins 4-8 -> PD Box S2401093 -> DCPD 003
    - S2500516 :: HAM3 ISIK REF A and REF B
         --Pins 5-9 -> PD Box S2401096 -> DCPD 005
         --Pins 4-8 -> PD Box S2401095 -> DCPD 006

And found that for every assembly,
    - Per D2400341, only pins 1,4,5,8, and 9 exist. See example picture of S2500514
    - All the anode (5 or 4) or cathode (9 or 8) pins are isolated from the case pin (Pin 1)
    - The anode pins for the two diodes (5 and 4) are isolated from each other
    - The cathode pins for the two diodes (9 and 8) are isolated from each other
    - Each diode's cathode to anode resistance (5 to 9 and 4 to 8) is in the ~2e6+/-1 [Ohm] = ~few [MOhm] as expected for the reverse bias operation we'll use the system.

The production PD assembly will function as designed without any shorts :: the negative reverse bias topology of the transimpedance amplifier and cable readout system will work!

I also attach pictures of the bags that aide assignment of serial numbers to assemblies.

Adding CHETA slow controls channels to DAQ EDC

Jonathan, Erik, Dave:

Following the installation of the CHETA Beckhoff chassis in the Vacuum Prep Lab we added the 724 AWC channels for itm[x,y] to H1EPICS_ECATTCSCS.ini for inclusion into the EDC.

at 12:22 I did a DAQ 1-leg and EDC restart. The EDC would not run, its systemd service was in a continual respawn state.

The number of EDC channels had increased from 59894 to 60618, and I remembered that there is a channel limit in the EDC code, which Erik verified was 60k.

Erik quickly built a new EDC with a 70k limit and installed this on h1susauxh56.

In the mean time I had put the H1EDC.ini file back and restarted 1-leg and EDC to get everything stable again.

At 13:22 we did a second round of DAQ+EDC restarts with the expanded channel list which was successful.

Installing h1sush6 IO Chassis

Fil, Dave, Erik:

I relocated the old h1sush2b IO Chassis from the CER to the MER. It is in the bottom of the SUS-HAM6 rack, at the same height as the neigboring h1sush7 and h1seih7.

I pulled a new MTP fiber from the IO Chassis to the MER patch panel, using the third port.

This IO Chassis currently has the cards left over after the h1sush2[a,b] consolidation in Dec 2025, we will populate it with the correct cards later.

Current layout:

No work was done on the front end computer in the MSR.

Later this week when the IO Chassis is powered up we will make the following changes in the MSR to the old h1susb2b computer:

1. disconnect the Dolphin cable from its IX card and verify the Dolphin switch port is fenced

2. move the MTP from the CER patch over to the 3rd port on the MER patch

3. run puppet to reconfigure the boot server to boot this computer as h1sush6 sans-Dolphin and only running h1iopsush5 model

4. boot the computer and verify the IO Chassis can be seen, the IOP runs and that the timing is good.

h1susb123 accumulated 4 DAQ CRC errors on the 1-leg overnight as reported by DC1, but none on the 0-leg.

All 4 models on h1susb13 increment their CRC counters at the same time. Normally we have zero CRC errors for weeks/months across the board.

I have cleared the CRCs and we will see if this trend continues.

It seems that whitening gains of some corner station QPDs were somehow set to zero on Friday Feb/20 17:22 UTC (09:22 PST).

Not sure why this happened, this seems to be earlier than the failed effort to update h1imcasc model (alog 89208). ALS QPDs, end station QPDs and all WFS RFs are good. Was something done to Beckhoff that day? 

I first noticed this for MC2 trans yesterday because it was interfering with IMC locking and WFS triggering. I checked all QPDs and WFS today and found that the following channels were affected. I restored them all to the value right before it was set to zero. 

Bypass will expire:
Tue Feb 24 11:57:58 AM PST 2026
For channel(s):
    H0:FMC-CS_FIRE_PUMP_1
    H0:FMC-CS_FIRE_PUMP_2
 

Workstations were updated and rebooted.  This was an OS packages update.  Conda packages were not updated.

WP13034

Fil, Dave, Daniel, Jonathan, Patrick, Sophie, Camilla,

Last week Fil and Daniel powered up the Cheta slow controls Beckhoff chassis in the MSR. It was sitting on a cart behind MSR02, connected to the MSR Chassis AUX-1 ethernet port with a short cat6 cable. Daniel added the AWS system to the SYS ECAT TCS CS PLC.

Today we moved the Cheta chassis into the Vacuum Prep Lab. It ethernt connection to the MSR chassis is now quite convoluted, a drawing can be found in D2600049

From the Cheta chassis the path is: cat6 cable to the wall RJ45 jack, building wiring connects this to the RJ45 patch panel in Room 163. Fil ran a cat6 cable from the patch, under the 163 floor, through a wall penetration to the CUR underfloor, then up to the wall mounted CUR CDS switch. This switch is connected to the MSR core switch, which in turn is connected to the FE switch in MSR04. A cat6 cable from this switch over to the Beckhoff chassis completes the link.

The link was tested in two stages. After Jonathan configured the core switch and the two edge switches to create a private VLAN connecting the switches, Fil moved the chassis into the CUR and connected it to the sw-cur-aux-stk port 1/1/7. I ran the above rack cat6 in the MSR from sw-msr-h1fe-stk 2/1/2 to the MSR chassis.

When powered down in the MSR DEV0 system went into a bad state. The H1:SYS_ETHERCAT_DEVICE_0_LOSTQUEUEDFRAMES channel (normally zero) accrued thousands of frames. The LOSTFRAMES (normally zero) became 13, the SLAVECOUNTACTUAL (normally 19) became zero.

When powered back up in the CUR, DEV0 status went green, the slave count went back to 19. The frame countered latched at their non-zero values. After Patrick reset them they stayed at zero.

Next Fil moved the chassis into the Vacuum Prep Lab, everything went green again and the frame counters stayed zero after reset.

At 17:26 Thursday 19feb2026 h1iopiscex had a timing glitch causing a TIM+ADC error in its state word.

At 20:00 I restarted all the models which cleared the error.

Rahul, Jeff, Oli

In December 2025 when we needed to compensate for the HAM1 DACs moving from 16- to 28-bit, we had decided to have FM10 in the COILOUTF bank be gain(1024), and put the remaining gain(4) upstream in multiple other places (88553). This led to our confusion today when we realized that when taking transfer functions for PM1 and JM3, the TEST banks had gone back to gains of 1 a couple weeks ago, and since we had damping off, the extra gain wasn't going through to the excitation. This might at least partially be why PM1 had dropped in magnitude, and why the JMs are so low in magnitude too.

To solve confusion, I've gone through PM1, RM1, RM2, JM1, and JM3 and removed the extra gain(4) that's in:
- DAMP bank FM4
- TEST bank gains (if still there)
- OPTICALIGN gains
- LOCK filter bank gains
Then I updated the gains in COILOUTF FM10 from gain(1024) to gain(4096).

I've sdf'd the values and loaded in the changed filter modules. I also committed the filter file.

*To remove future confusion about the difference in value of the "28BitDAC" filter module in COILOUTF FM10, I am going to go through all the suspensions and change the name of that filter from "28BitDAC" to be something like "16to28Bit" or "18to28Bit" depending on the previously used DAC bits

DAQ was restarted around 12:02 PM  PST after restarting h1ascimc. 

I added this shutter (shutter H1:SYS-MOTION_C_SHUTTER_M) to the main shutters screen at sitemap->LSC->Shutters. I also added a menu button that takes you to the control screen to the sitemap->IOO->JAC Overview screen, see pic.

Jennie W, Ryan S

Summary: Ryan and I updated the JAC and IMC ASC models. We installed JM3 yesterday and so now the IMC cannot use the PSL PZT mirror as an alignment actuator. I have committed the changes to the svn but erik and dave will do some checks tomorrow before they commit to the revision locked version of the model and restart the DAQ. So changes are not 'live' yet.

The edits were made to h1ascimc.mdl which has top level blocks for IMC and JAC.

The JAC top level model sends signals directly to the PSL PZT mirror and these degrees of freedom are swapped as the PSL PZT basis P and Y are switched before input to the JAC due to the HAM1 input periscope.

I took out the feedback paths for PZT_P and PZT_Y that come out of the IMC block. The picture shows the old config and I have highlighted what I removed.

At the top level, IMC no longer sends signals to the PZT but instead to JM3. On the top level diagram, the signal JM3_P is sent via PCI cards to the channel "H1ASC-JM3_YAW_SUSHTTS" as pitch in the JAC basis is yaw in the IMC basis due to the HAM1 output periscope. The picture shows the old config and I have highlighted what I swapped.

The signal JM3_Y is sent via PCI cards to the channel "H1ASC-JM3_PIT_SUSHTTS" as yaw in the JAC basis is pitch in the IMC basis due to the HAM1 output periscope.

Within the IMC top names block I removed the output channels for the PZT from the WFS feedback path, we already had paths to feedback to JM3 within this path. The picture shows the new config.

I removed the PZT locking path from the LCKIN block and replaced it with one for JM3. The picture shows the new config. I am not sure we ever use this path (which is for dither asc control of the IMC) in the first place so maybe this was unneccessary.

I also removed the channels H1:IMC-PZT_YAW_OUT and H1:IMC-PZT_PIT_OUT from the DAQ channel list for the IMC model.

Or, rather, a better JM3 integration and PSL unintegration.

I made a temporary IMC_WFS_MASTER and IMC_WFS_OUTMATRIX_kk screen such that it's easy to route IMC WFS signal to JM3, not the PSL PZT, because I wanted something that works now.

However, right after I made what looks to be an OK screen, I realized that this doesn't work. PIT signal should be routed to JM3 YAW and vice versa. No fully-working IMC WFS until the next model update.

In addition, earlier today Daniel suggested to nuke PSL PZT from the IMC ASC (good idea).

If you want to revert back to the old medm, copy the backup

/opt/rtcds/userapps/trunk/asc/common/medm/imc/IMC_WFS_MASTER_BAK_20260218.adl 

to

/opt/rtcds/userapps/trunk/asc/common/medm/imc/IMC_WFS_MASTER.adl