WP 6635
FRS 8091
This morning the 24MHz RF oscillator source for EY showed a timing error. Chassis was powered cycled and timing error cleared. RF output levels for unit are within spec. Richard did noticed the readback signals for this unit were incorrect. Unit is currently in the EE lab for troubleshooting.
S1000581
The RF Source (24MHz) is now reinstalled at EY. Both the timing and readback signals errors have cleared.
1. Timing error for RF source EY was reported.
2. Unit was power cycled and timing fiber reseated. Unit locked according to front panel led lights.
3. The readback frequency, error, and control signal all displayed incorrect values in MEDM.
4. Looked at RF levels and frequency outputs. All within spec.
5. Unit was brought back to EE lab.
6. The input IC buffer on the timing interface 1 PPS locking board was replaced. We later convinced ourselves IC buffer never had an issue.
7. The FPGA on the timing slave was reprogrammed. We used the same Version 4 subversion 118 code.
8. Unit was reinstalled at EY. Unit locked within 5 minutes and all readback signals now show expected values.
F. Clara, R. McCarthy, M. Pirello