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Reports until 13:11, Thursday 28 September 2017
H1 SUS (CDS, DetChar, ISC, SQZ, SUS, SYS)
jeffrey.kissel@LIGO.ORG - posted 13:11, Thursday 28 September 2017 (38827)
Summary of Front-End Code Model Changes to Accomodate SQZ Suspensions; VOPO, ZMs, and OFI (Impacting RMs and IMs)
J. Kissel, D. Barker, D. Sigg

Dave and I've made all the necessary model changes to account for re-shuffling of the suspension electronics (see LHO aLOGs 38796, 38753, 38778). Those changes are summarized in the screen-capture below, and follow the ADC / DAC arrangement sketched out by Daniel in D0902810-v8 and D1002740-v7. "Current" was the O1 / O2 configuration, "New" is the O3 configuration. The numbers following the model names are the DCUIDs.



In words, I've: 
- Created coil driver monitors in h1susauxh2 and h1susauxh56 for all new suspensions, re-arranging as mentioned above
    - Updated the FOUROSEM_MONITOR_MASTER to use full filter banks instead of just test points and EPICs Monitors
    - Changed the stored channel name list to include the "VOLTMON_??_OUT" needed for filter banks as opposed to the test point which was just named "VOLTMON_??""
    - Only IMs, RMs, and OMs, use this library part so there's no need to recompile other susaux models
- Changed the PR3 optical lever ADC channel assignment in the h1susim model on the h1sush2b computer and removed the HAM2 table optical lever (these were picked up by h1sush2b sent out over the dolphin PCIE network to h1sush2a for consumption in the h1suspr3 model)
- Removed the OMs for the h1sushtts model (but the RMs remained), and changed the h1sushtts model to run on the second user model core (specific_cpu=3) of h1sush2b computer
    - Changed the ASC control IPC receiver channels from shared memory (SHMEM) to over the dolphin PCIE network (PCIE)
    - Terminated all of the OM inputs to the HTTS ODC vector
- Installed the OMs into the h1susomc model of h1sush56 computer
    - Brought in an ADC1 block for the OMs
    - Changed all the ASC control IPC receiver channels from SHMEM to PCIE
    - Did NOT create any new ODC vector, so terminated all the status output from each HSSS_MASTER block
- Modified the h1asc model IPC outputs for the RMs and OMs to use PCIE instead of SHMEM
    - Found that IM4 TRANS (sent by h1ascimc on h1asc0) was never received by the h1asc model (on h1asc0), so we hooked up the receiver... but are still suspicious how initial alignment ever worked without this... 
- Created a new model h1susopo
    - Installed ZMs using HSSS_MASTER.mdl
    - Created new library parts VOPO_MASTER.mdl and OFIS_MASTER.mdl, and installed those as control in top-level model

I attach a bunch of screenshots of tghe finalized models to guide the eye -- and to guide the install at LLO.

The following models have been compiled, installed and are running:
 - h1susauxh2
 - h1susim
 - h1sushtts

The following have been compiled, but we'll wait until next Two Tuesday to install them (due to work on replacing the SRM, and our need for more electronics)
 - h1susomc
 - h1susopo
 - h1susaush56
 
Next up -- MEDM screens, and especially, re-populating the RM's control systems.

Images attached to this report
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