Jim, Dave:

We power cycled the h1seiex system as part of Jim's low frequency noise mitigation study. The sequence was:

remotely: stop all models and power down h1seiex cpu.

At EX, power off: IO Chassis, AI chassis (qty 2), AA chassis (qyt 4)

The power up sequence was:

IO Chassis, AA chassis (qty 4), h1seiex cpu, AI chassis (qty 2)*

* - remember that the 16bit DACs output 10V on power-up until the front end computer is energized, so the AI chassis are the last to be powered up.

The h1iopseiex model came back with a slightly negative IRIG-B drift, which cleared after about 5 minutes at which point we could clear the IOP and model watchdogs.

Jim will take measurements to see if the power cycle has fixed anything.