J. Kissel, J. Driggers, H. Yu

While I was exploring signals for balancing the coils fro MC2, I found that we were sending the same control IMC ASC P and Y signals to all three stages of MC2 (see 3rd attachment showing ASDs of test points just upstream of the LOCK filter banks for stage, after the hierarchy split). Which stage gets what signal can be controlled by output switches which are just downstream of the LOCK filters for each stage (see green highlighted switches on the overview screen; 4th attachment). 

Trending reveals that, while the M3 stage output switches had been turned ON on Jun 21 2018 at 14:36 PDT (21:36 UTC), where they had been OFF up until then during and since O2. The M2 stage output switches are a little bit more confusingly ON during O2, and only briefly off between Jan 2018 and Feb 2018 -- but there have been no distribution filters (typically a simply integrator) on the M2 or M1 stages for P and Y which delineates at what frequency the control signal has authority at each stage. See 1st attachment, showing a 360 day trend, which takes us back to Jul of 2017, during O2.

Even more suspiciously, there *is* an "1:0", 1 Hz integrator in each FM2 bank of MC2's M1 LOCK bank, but they haven't been turned on ever (at least not back through prior to the beginning of O2). See 2nd attachment, showing the SWSTAT for this filter bank. The bank is alternating between having the following states:

    SWSTAT            What Switches 
    Binary Value      Are ON

    32768             DEC
    33792             DEC, INP
    36864             DEC, OUT
    37888             DEC, INP, OUT    (The apparent nominal state during O2)

The SWSTAT never goes higher that 37888, implying that the filter state INP, FM2, OUT, DEC, which is 300034, never happened. I checked back as far as 2016, and didn't see this state ever occur.

For now, pending further investigation, we're leaving the H1SUSMC2 M2 and M3 stages P and Y output switches OFF, and Jenne accepted these changes into the SDF system.