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Reports until 15:07, Friday 10 August 2018
H1 CDS
david.barker@LIGO.ORG - posted 15:07, Friday 10 August 2018 - last comment - 15:16, Friday 10 August 2018(43359)
h1sush2a time glitched, restart of all models fixed it

Similar to last Friday (alogs here Link and here Link) h1sush2a had a timing glitch which the IOP could not recover from and the DAC drives were subsequently zeroed.

This time the user models detected an ADC timing error (see attached dmesg output) which was not the case last Friday.

After the IMC was put into a safe state, I stopped the models and ran the IOP model by itself for several minutes to verify its timing. I then started the mc1, mc3, prm and pr3 models one at a time, verifying the IOP IRIG-B each time. There is no repeat of the IRIG-B excursion this time. Why this has happed twice in one week with no activity in the CER is still a mystery.

Autocal of the 18bit DACs are correct, once again the 3rd DAC runs slightly long in its cal cycle.

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david.barker@LIGO.ORG - 15:16, Friday 10 August 2018 (43360)

Attached image shows the three separate 18bitDAC autocal blocks since h1sush2a was rebooted last Friday 3rd August 2018.

The first block is soon  after the reboot when the models were auto-started The second block is 3.01 hours later when a model restart was required (the IOP IRIG-B excursion had almost completed). The third block is today's restart, 7.20 days after the reboot.

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