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Reports until 17:19, Saturday 29 September 2018
H1 SQZ (SQZ)
nutsinee.kijbunchoo@LIGO.ORG - posted 17:19, Saturday 29 September 2018 - last comment - 17:19, Sunday 30 September 2018(44242)
SQZ locking loops automated

Haocun, Nutsinee

 

Almost every locking loop in SQZ land is now automated. I haven't created a manager node yet so you'll have to lock each loop by hand. Starting from SHG>OPO>PLL>FREQ>CLF (necessary for working on 3MHz locking loop).

 

SQZ_OPO Guardian will feed beat note error signal to laser temperature when it's in DOWN and feed PZT offset to pump laser temperature when it's LOCKED_ON_DUAL (or LOCKED). It will also disengage EOM when it's rail and stay in the CHECK_EOM state until somebody close it by hand (to make EOM relock itself requires a little more thinking. It probably could look at PLL guardian state).

 

SQZ_PLL (phase locking loop) will take care of beat note locking using OPO PZT once the OPO is locked (with TTFSS). SQZ_FREQ will feed (frequency) error signal from OPO common mode board fast path to OPO PZT once SQZ_PLL is locked.

 

When SQZ_OPO is down it will also take PLL, FREQ, and CLF down with it. Once OPO is relocked everything down the path still has to be locked by hand. PLL will complain if OPO isn't nominal and FREQ will complain if PLL is not nominal.

 

Neither feed forward nor 80MHz VCO is touched by Guardian yet. Everything worked repeatedly at least all day today. Will try to leave everything locked overnight.

 

All the SQZ guardians window can be found under SQZ GUARDIAN OVERVIEW button. I will create a compact overview of these guardian windows on SQZ_OVERVIEW later.

 

Terry also made a nice diagram of our current locking scheme. See attachment. Hopefully it'll be in the dcc soon.

 

Next: Lock the LO.

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nutsinee.kijbunchoo@LIGO.ORG - 17:19, Sunday 30 September 2018 (44248)

Attached a screenshot of the new screen. Dash lines indicate independence. Arrows indicate flow/order of locking (eg. PLL and CLF can happen at the same time but FREQ has to happen after PLL is locked). In the end there should be a master node that controls everything from OPO to LO.

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