Georgia Craig Dan Brown Hang Sheila Haocun Jenne
Summary: We can get to DC readout, but are not very stable once we transition to DC readout, and we probably need to double check the DARM loop shaping in the transition to DC readout.
- Today DRMI locking is better than it was yesterday. PRMI has to be well aligned for DRMI to grab lock, this seems more critical than in the past.
- Jenne logged a scan of SRCL offsets we did. 45579 We haven't had a chance to double check the calibration of this. We've removed the SRCL offset from the DRMI locking.
- We have had difficulty with the state OFFLOAD_DRMI_ASC, similar to what we saw last night. 45565 The problem is that when we turn off the AS45->BS feedback and try to re-engage AS36->BS there is sometimes a large transient. This might be worse when the alignment of DRMI isn't great. Jenne and I tried adding the -20dB filter and turning off the integrator and for a gentler engage of the loop. Later Craig and Georgia edited this again to also turn the inputs off and back on. This still breaks the lock sometimes.
- Jenne moved the alignment offsets around and found a set that gave us a recycling gain of 48-49 with 2W input power. 45584
- After that Hang reset the green QPD offsets and the camera offsets, and I went to ISCT1 and realigned the beams onto the cameras and the COMM and DIFF beatnotes. The COMM beatnote is about 2dBm, DIFF is about -9dBm.
- the violin mode we are calling ITMY move 7 seems to have had a phase change, we have damped it with a sign flip consistently today so we put this in the guardian.
- We had several locklosses trying to power up to 10W. Georgia will add a comment about that. THe problem was possibly the notch mentioned in Jenne's alog that she says cannot be used to power up.
- Haocun checked that the squeezer alignment is still good with the change in IFO alignment.
- We had trouble staying locked long at DC readout, so we check MICH, PRCL, SRCL loop gains just before the transition. They all seemed fine.
- We also checked the phasing of POP45, Craig changed it from -5 degrees to +7. We also remeasured the POP9I to SRCL matrix element, which we found to be a factor of 5 smaller than what we had in the past, 0.0047 is the new value we found. We tried this once but haven't added it to the guardian because in the past we have seen this changing from lock to lock.
- We weren't able to stay locked for long on DC readout, and have also lost lock in the transition to DC readout. Craig looked at one of these locklosses and saw that it lost lock while the gain was increasing for DARM
- If the morning team is in the same position we are in tonight, it might be a good idea to check the DARM loop gain during some of the loop reshaping that happens in the transition to DC readout.
Here is a comparison of POP build ups in counts, un-normalized now and before the last few weeks of work.
| |
|
before vent and pre-loading |
now |
| PRMI+ALS |
POP18 ERR |
148 |
109 |
| |
POP90 ERR |
174 |
133 |
| DRMI + ALS |
POP18 ERR |
163 |
136 |
| |
POP90 ERR |
30 |
29 |
The last few locklosses we've had from DARM_TO_DC_READOUT or INCREASE_POWER have been fairly fast. It looks like the first thing that shows up is a 20Hz oscillation in SRC2 ASC, DHARD, DARM and SRCL.
I'm attaching plots from the last lockloss (2018-11-30_07:49:12 UTC), in case that's useful for the morning crew. First plot is ASC signals, second plot is LSC signals.
Is the AS36 phasing still okay? Could have changed with different TCS.
Daniel: It was not, but now is. I had the same thought, and checked it this morning (although didn't log it until mid-morning).