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Reports until 23:57, Thursday 29 November 2018
H1 ISC
sheila.dwyer@LIGO.ORG - posted 23:57, Thursday 29 November 2018 - last comment - 13:54, Friday 30 November 2018(45588)
locking progress today

Georgia Craig Dan Brown Hang Sheila Haocun Jenne

Summary: We can get to DC readout, but are not very stable once we transition to DC readout, and we probably need to double check the DARM loop shaping in the transition to DC readout. 

Here is a comparison of POP build ups in counts, un-normalized now and before the last few weeks of work.  

    before vent and pre-loading now
PRMI+ALS POP18 ERR 148 109
  POP90 ERR  174 133
DRMI + ALS POP18 ERR 163 136
  POP90 ERR  30 29
Comments related to this report
georgia.mansell@LIGO.ORG - 00:16, Friday 30 November 2018 (45590)

The last few locklosses we've had from DARM_TO_DC_READOUT or INCREASE_POWER have been fairly fast. It looks like the first thing that shows up is a 20Hz oscillation in SRC2 ASC, DHARD, DARM and SRCL.

I'm attaching plots from the last lockloss (2018-11-30_07:49:12 UTC), in case that's useful for the morning crew. First plot is ASC signals, second plot is LSC signals.

Images attached to this comment
daniel.sigg@LIGO.ORG - 10:55, Friday 30 November 2018 (45592)

Is the AS36 phasing still okay? Could have changed with different TCS.

jenne.driggers@LIGO.ORG - 13:54, Friday 30 November 2018 (45595)

Daniel:  It was not, but now is.  I had the same thought, and checked it this morning (although didn't log it until mid-morning).

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