J. Kissel
FRS Ticket 12201

Inspired by the problem with charge measurements this morning (LHO:46619), I took a look at test points of the DAC output for SUS ETMX L3's UL ESD quadrant during a stable state of lock acquisition (specifically on ALS DIFF, and thus NOT saturating) in order to help understand at what point of requested digital counts that the DAC saturates. Attached are the results.

The DC values of the transfer functions are as follows:
Request  > USER Out      0.966245
Request  > IOP Out       1.00299
USER Out > IOP Out       1.03802

Why there's this gain divide-down then back-up between the Request, USER Out, and IOP, I don't know. 
However, it does mean that when requesting, say 400000 ct out of the DAC, it'll actually send out 400000 * 1.00299 = 401196 ct out of the IOP.
That would also mean that a digital request of the theoretical maximum of the 20-bit DAC, 524288 ct, would actually try to send out 544221.42976, i.e. too much by ~19933. Thus the real saturation limit is 2^19 / 1.03802 = 505084 ct, i.e. 3.6% less than you'd expect.


I also attach the DTT template if one needs to repeat this test (note that only the request channels are stored in the frames, so the test must be done live).

Channel map for SUS ETMX L3's UL ESD quadrant:
Request    H1:SUS-ETMX_L3_MASTER_OUT_UR
USER Out   H1:SUS-ETMX_MDAC3_TP_CH3
IOP Out    H1:IOP-SUSEX_MDAC4_TP_CH3