Reports until 14:48, Friday 25 January 2019
H1 ISC (Lockloss)
jonathan.richardson@LIGO.ORG - posted 14:48, Friday 25 January 2019 - last comment - 17:51, Thursday 31 January 2019(46642)
Is dynamic range of ETMX ESD a source of glitching?

I've examined the time series of the control signal to the ETMX ESD, which is being used alone to control the DARM degree of freedom. There is some evidence the dynamic range might be too small. Every time the ESD control signal nears the end of its dynamic range (+/-2^19), an IFO glitch occurs, but the ESD signal does not rail every time a glitch occurs. This would suggest that an insufficient ESD actuation range is, at worst, one of several causes of glitching. It's worth investigating further.

I've written a code for scanning past actuator-channel data and identifying saturation events. It generates an ASCII catalog containing the timestamp and value of every saturation occurring within a specified time range. It filters data based on Guardian state to only include data taken during "low noise" operation.

https://git.ligo.org/jonathan.richardson/dac_saturation_scanner

The figure below was generated using this code for a 6-hour lock on Jan. 13.

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Comments related to this report
andrew.lundgren@LIGO.ORG - 08:25, Monday 28 January 2019 (46668)DetChar
If the overflow caused the glitch, we'd expect the drive value to already be somewhere near 2^19, and for the glitch to happen when it accidentally goes past the overflow value. Instead, the DAC value is generally between +/- 100K. Then during the glitch it has a fast excursion to above 500K in a millisecond.

To look at one of the events, you can grab the times of overflows from the summary pages, e.g. this link. FEC 88 3_4 is one of the ETMX ESD quadrants. The attached plot is a zoom in of the drive signal. At least in this case, it's much more likely that there's a short loud glitch that causes the feedback to overflow, rather than the other way around. This was also the case with overflows that we investigated with the 18-bit DAC on the ESD.

One cause of glitches that worries me is something above the Nyquist sampling rate of this channel, like PI damping. I don't know how RMS that has, or what it would look like if that caused an overflow.
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john.zweizig@LIGO.ORG - 17:51, Thursday 31 January 2019 (46732)DetChar

Note that when the DAC was changed from 18-bits to 20-bits a x4 gain stage was added to a filter bank (see alog) apparently to avoid changing all the other constants. I haven't traced out the model, but this would suggest that the saturation would be at 2^17 as before rather than 2^19. There is still a discrepancy between the apparent glitching at ~1.0 rather than ~1.3 but it is much more consistent with a saturation and may be related to the reduction in maximum range discussed elsewhere.