J. Kissel ECR E1900197 / IIET Ticket 13175 WP # 8277 I've taken Joe's instructions from LLO (see LHO aLOG 46978), and updated the h1calcs front-end code by compiling with updated library parts and c-code in the userapps repo, /opt/rtcds/userapps/trunk/cds/common/src/COH_GATE.c /opt/rtcds/userapps/trunk/cal/common/models/CAL_LINE_MONITOR_MASTER.mdl /opt/rtcds/userapps/trunk/cal/common/models/CAL_CS_MASTER.mdl I've also received his updates to MEDM screens, /opt/rtcds/userapps/trunk/cal/common/medm/CAL_CS_TDEP_OVERVIEW.adl /opt/rtcds/userapps/trunk/cal/common/medm/CAL_CS_TDEP_F_S_OVERVIEW.adl /opt/rtcds/userapps/trunk/cal/common/medm/CAL_CS_ACTUATION_FUNCTION.adl but noticed that he missed changing over the input labels and channels at the upper level of TDEP_OVERVIEW's calculation to the f_s and Q from LINE4, so I've switched things to LINE1. I've also added labels to the TDCF outputs just for extra readability of the screen. These changes have been committed to the repo. As a result of these changes, we expect: - Bug fix in the application of kappa_U and kappa_T to the CFTD_DELTAL_EXTERNAL path. - Update to the gating algorithm to better match the GDS pipeline. - We expect that the calculation of f_s and Q will now be restored (because we're using the "actuator" PCAL line at 17.10 Hz, instead of the now-defunct 7.93 Hz line). - Bug fix in some of the screen indications of what goes where (especially with kappa_U / kappa_P / kappa_T application in the CFTD path). The reference model parameters (i.e. what the calibration group calls "EPICS RECORDS") at the 17.1 Hz line frequency have already been installed (they came with the 2019-04-16 reference model push). Also, the phase modification to account for the clock-cycle difference between the corner station and end station computers, kept in the channel H1:CAL-CS_TDEP_PCAL_LINE1_PCAL_DEMOD_PHASE, was also installed during the reference model push. So -- the only thing I needed to change for switching over to the PCAL_LINE1 was to change the channel H1:CAL-CS_TDEP_D2N_SPRING_PCAL_FREQ to be set to 17.1. I've confirmed that we at least have all former TDCFs back up and running and are functional. Stay tuned regarding f_S, Q_s, and the CFTD path.