The red timing bit on the h1iopasc0 model is a latched signal, it was raised when the IOP momentarily ran long (17uS) at 06:37 PST this morning. Since this error is not repeating, we will wait until the next lock-loss to clear it. In the attachment, the cpu processing time and the model's state-word are trended, showing the 2nd bit of the state word (the timing bit) was raised when the cpu ran out to 17uS during one cycle of the 65536 cycles in that second.