jeffrey.kissel@LIGO.ORG - posted 15:35, Thursday 04 November 2021 - last comment - 09:15, Friday 05 November 2021(60532)
One Mystery Solved: Recall, A+ HSTSs, e.g. H1SUSFC1, have 20-bit DACs not 18-bit DACs -- Installed gain x4 Compensation in COILOUTF Banks to Compensate
J. Kissel, B. Weaver, R. Kumar Another mystery we'd been confused by while commissioning H1SUSFC1 was why all M1 to M1 transfer functions were showing a pretty large factor reduction in magnitude (somewhere between 3 and 5 -- roughly the same factor across all DOFs, which is usually indicated of an electronics issue) between when FC1 was tested with PR2 electronics vs. when it was tested with its own, brand new, production electronics. I didn't "put two and two together to get 4x" until this morning when taking transfer functions, watching the DAC output not saturate at 131072 [ct_peak]: All new A+ HSTSs have been built with 20 bit DACs for all stages based on the success of changing out the ETM TST and PUM stages from ECRs E1800306 and E1900216. It didn't make it in to any ECR, or DCN, or RODA, but it's clear from the wiring diagram (D2000202, Page 5) that this is so. In fact, I've been told by the great Rich Abbott, that "the plan" is that in the future, whenever 18-bit DACs fail, we'll be replacing them with 20-bit DACs. As such, instead of changing all the control design upstream -- where different sets of people often design each functional path at different times, and love to copy-and-paste from like-SUS to like-SUS 'cause its easy -- I've now done what I did for the ETMX ESD when we installed 20-bit DACs (LHO:44905), and added a gain of 2^20 / 2^18 = 4 in to FM4 of all of FC1's COILOUTF banks, called "20BitDAC." I've confirmed that this is what needed by calibrating this morning's transfer functions of FC1 (see LHO:60530) with the extra factor of 4. Only *after* confirming this, and also confirming that the damping loops work *a lot better* when they have the as-designed amount of DAC gain, did I install this filter. So -- all *future* transfer function takers should not need to think about this anymore. I've accepted FM4 as ON in FC1's SDF safe.snap file, and committed the H1SUSFC1.txt filter file to the userapps repo. Attached are screenshots of what the COILOUTF banks look like for M1, M2, and M3. Note, FM4 is chosen because it does not interfere with either the M1 (top driver), M2 (TACQ driver), or M3 (TACQ driver) front-end controlled coil driver response compensation.
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"Shave and a haircut--...."
"... TWENTY BIIIIIIIIIIIITTTTSSSS!" :-D Correction to my statement "It never made it to an ECR, DCN, or RODA" and citable info surrounding the discussion of "the plan": Looking through the IIET Ticket list this morning for other things, I see the following: IIET Ticket 20828: ECR: Upgrade remaining SUS 18-bit DACs to 20-bit It doesn't have a companion DCC entry yet, but the ticket is still fresh, and it will, I'm sure, eventually. I guess technically this doesn't cover the A+ HSTS, but since there's already several ECRs requesting the upgrade to 20-bits, I think the sensitive A+ SUS (i.e. the HSTS FC1 and FC2) were just included in the bunch. Other 20-bit DAC upgrade ECRs: what they cover -- and whether they've been implemented at LHO: E1800306: "Upgrade ETM ElectroStatic-Drivers to use 20-bit DACs" (nominally all QUADs) -- only H1SUSETMX and H1SUSETMY E1900216: "Replace 18-bit SUS PUM DACs with 20-bit DACs" (Nominally L2 or M2 stages all QUADs, BSFM, HLTS, HSTS) -- none yet implemented, aside from the A+ HSTSs FC1 (and eventually FC2) IIET Ticket 20828: ECR: Upgrade remaining SUS 18-bit DACs to 20-bit (All the rest of SUS stages that have 18-bit DACs) -- none yet implemented, aside from the A+ HSTSs