J. Kissel, others

Since I'm beginning to be asked to "calibrate" the DARM loop again, it's a good time to check in on what the status of things are currently. 
Namely, this is a report of the state of the DARM loop and various things we've come to know that impact it during today's nominal low noise, with HAM5 - HAM7 gate valve open, lock stretches:

(In short: we're not where we want to be... yet, and there's plenty of configuration choices that are not even stable from lock-stretch to lock-stretch)

For there record, there were three nominal low noise lock stretches that this covers, and even me asking the status of things trigger us to remember to change thing, so the things that affect the DARM loop changed between these locks.
   "First": 2022-05-23 21:28 UTC to 22:05 UTC (with calibration and ADS lines off 21:36 UTC to 21:01 UTC)
   "Second": 2022-05-23 22:48 UTC to 22:30 UTC (with calibration and ADS lines off 23:11 UTC to the end)
   "Third": 2022-05-24 00:16 UTC to 00:55 UTC (with calibration and ADS lines off from 00:40 UTC to the end)

Power
    50 W from the PSL
    40.3 W into PRM
    
    Power Recycling Gain PRG ~54.4

ASC
    Running on REFL WFS for INP1, PRC2, and CHARD (rather than POP WFS for INP1 and PRC2)
    ADS loops are OFF during calibration measurements measurement.
        Turned them on ~20 minutes later, and they show quite a bit of drift has happened.
    CHARD loop has some sort of uncharacterized instability ... working on it

TCS
    Two ETM Ring Heaters ON
        EX 0.44 W
        EY 1.00 W
    Only one C02 laser on:
        2.6 W Annular on IX

LSC
    DARM Actuator Config: "split"    
        EY UIM State 2 (low pass on) << should be 1.0 << switched by the second lock to 1.0 (LHO:63282)
        EY PUM State 1 (one low pass on) << should be 3
        EX TST State 2 -- low-voltage low noise. (normal)

    Between 1st and 2nd lock stretches, switched from controlling LSC MICH, PRCL, and SRCL with in-air POP to in-vac POP.

    No intentional SRCL offset is being applied

OMC Electronics / Violin Mode Mitigation:
    This morning, switched back to the OMCA (nominal, well-characterized) Whitening Chassis path, and switched to that compensation.

    Low DARM offset to squeak a bit more ADC range out of the DCPDs while violin modes are still high-ish. << this was switched by the third lock (LHO:63288)
    (15 mA on the PDs instead of 20 mA)
    (7.3 pm vs sqrt(7.3^2 * 20/15) ~ 8.4 pm)

The few calibration measurements I got started ~30 minutes after hitting requested 50 W input.
The broadband PCAL injection was *before* the switch to in-vac POP, and *before* the ETMY UIM state switch to State 1.
The swept-sine PCAL injection was *after* the switch to in-vac POP, and *after* the ETMY UIM state switch to State 1.