Reports until 12:55, Tuesday 14 May 2013
H1 CDS
james.batch@LIGO.ORG - posted 12:55, Tuesday 14 May 2013 (6356)
Power cycle timing slave in LVEA
In an effort to correct timing errors on the test stand computers in the LVEA (problem since the power outage early April), I powered off h1oaf0, h1susquadtst, h1susbstst, and h1seitst computers and I/O chassis, then power cycled the timing slave and IRIG-B.  I waited for the the timing slave to sync up and the IRIG-B unit to start displaying the correct time.  Then the I/O chassis were powered on, followed by the computers.  

With the exception of h1susbstst, the models started up with no timing errors.

h1susbstst started with a large IRIG-B time offset, and the models showed timing errors.  I powered the computer down, power cycled the I/O chassis, then powered up the computer again.  The timing remained in error.  I killed the models, then started the IOP model by hand.  The timing was off, and the ADC and DAC indicators were all red.  The IOP ran for several seconds, then the GPS time stopped incrementing.  I powered off the computer and I/O chassis and gave up.  This will take some more troubleshooting.

Also, I moved the IRIB-B feed for the x1dc0 computer on the DAQ test stand to the DTS IRIG-B unit in the H2 Electronics room.  It was being fed from the LVEA IRIG-B unit by a very long cable, left over from the H2 DAQ system.