jeffrey.kissel@LIGO.ORG - posted 10:49, Tuesday 23 August 2022 - last comment - 13:10, Tuesday 23 August 2022(64620)
SUS AI chassis Cabling Assignments Changed to Better Utilize 20-bit DAC Channels: User Model Changes and Physical Cable Rearrangement Complete
D. Barker, J. Kissel, A. Jennings, F. Clara IIET Ticket 24632 ECR E2200324 WP 10634 This is Part I of the aLOGs covering the re-arrangement of SUS AI chassis output cable assignments in order to better utilize the 20-bit DACs we installed a few weeks ago (see LHO 64274 and 64368) (or will install in the future) on the QUADs, BS, SR3 and MC2. I'm finished the top level model changes that are required to execute ECR E2200324, to match the shift in analog cabling outputs to the corresponding AI chassis. Check out the diagrams in the ECR itself, specifically E2200324-v1_QUADCableRearrangment_for20bitDAC.pdf, to help get a better feel for what's changing in analog land. Fil has completed all of the cable re-arrangments exactly as described in the above referenced diagram. In digital land, that means we must rearrange the digital inputs to the digital representation of these DACs. In a lot of cases, after re-sorting which stage's control goes to which DAC, it means we can clean *up* the model, and pull out DAC cards usage where signals have been split across DACs. Dave built, installed, and restarted all the affected user models. Because we added and removed DAC cards from models, it also meant we needed to restart the IOP models that govern these user models (without change to them). *That* meant we had to restart all user models (without change to them) that are governed by those IOP models. The IOP model restart is necessary to "clear out" the declaration / assignment of DAC usage in the IOP process to avoid conflict. Note: while the ECR's diagram suggests that some cable swaps and DAC upgrades as "MAYBE ALSO," we only executed the MAYBE ALSO *cable* changes (and corresponding necessary model changes). We did *not* upgrade / change any DAC cards today / yet. Just to make the aLOG a little more tolerable / legible, I'll attach screenshots of the changes in the comments below that will be grouped to match the changes in analog land. Said in words, here're the consequences: Without out physically changing any cards in any IO chassis - At both end stations, ETM L1 (UIM) stages got *upgraded* to be using 20-bit DAC channels. - At both end stations, 2/3rds of the TMS M1 (TOP, F1F2F3LF OSEMs) stages got re-*downgraded* to be using 18-bit DAC channels. - BS M2 stage got *upgraded* to be using 20-bit DAC channels. - 2/3rds of the BS M1 (TOP, F1F2F3LF OSEMs) stage got re-*downgraded* to be using 18-bit DAC channels. - ITMY L1 remains driven by an 18-bit DAC, but it's 4 channels are now grouped with ITMX L1's 4 channels, such that *when* we want to upgrade the ITM L1 UIM stages to a 20-bit DAC, it'll be just a one-card change instead of 2. Though ITMY's L1 remains driven by *an* 18-bit DAC, it's being driven by a *different* 18-bit DAC channels than before. - SUSB123's DAC 5 remains an 18-bit DAC card (but when upgraded, that will upgrade both ITMX and ITMY L1 [UIM] stages). - SR3's M2 and M3 stages remain driven by an 18-bit DAC, but their channels have been grouped to be on one 18-bit DAC rather than being split across two. Though both SR3 M2 and M3 stages are still driven by *an* 18-bit DAC, they're are being driven by a *different* set 18-bit DAC *channels* than before. - SUSH56's DAC 3 and DAC 4 remain as 18-bit DAC cards. - MC2's M2 and M3 stages remain driven be an 18-bit DAC, but their channels have been grouped to be on one 18-bit DAC rather than being split across two. Though both MC2's M2 and M3 stages are still driven by *an* 18-bit DAC, they're are being driven by a *different* set 18-bit DAC *channels* than before. All corresponding top-level model changes in the comments below, to /opt/rtcds/userapps/release/sus/h1/models/ h1susetmx.mdl h1sustmsx.mdl h1susetmy.mdl h1sustmsy.mdl h1susitmy.mdl h1susbs.mdl h1susitmx.mdl h1sussr3.mdl h1susmc2.mdl have been committed to the above mentioned location in the userapps svn repo. Stay tuned for more parts!
Here're the top level model changes for h1susitmx, h1susbs, and h1susitmy that are all on the h1susb123 IO chassis. - in h1susitmx (before vs. after) - Add DAC_1, card_num=1, 18-bit DAC to the model - Move ITMX R0 from DAC_5, card_num=4 to use channels 4-7 of DAC_1, card_num=1, 18-bit DAC As mentioned above, this means there's no change, nominally, to the function of either stage, but it lines up ITMX L1 to be easily upgraded to an 20-bit DAC eventually. - in h1susitmy (before vs. after) - Add DAC_5, card_num=4, 18-bit DAC to the model - Move ITMY L1 from channels 4-7 of DAC_1, card_num=1, 18-bit DAC to use channels 0-3 of DAC_1, card_num=1, 18-bit DAC As mentioned above, this means there's no change, nominally, to the function of either stage, but it lines up ITMY L1 to be easily upgraded to an 20-bit DAC eventually. - in h1susbs (before vs. after) - Move BS M2 ULLLURLR "up" to use channels 4-7 of DAC_2, card_num=0, 20-bit DAC. - Move BS M1 F1F2F3LF "down" to use channels 0-3 of DAC_3, card_num=2, 18-bit DAC. - Move BS M1 RTSD "down" to use channels 4-5 of DAC_3, card_num=2, 18-bit DAC. As mentioned above, this upgrades BS M3 ULLLURLR OSEMs, and downgrades BS M1 F1F2F3LF OSEMs.