[Sheila, Craig, Me]

Sheila posted this alog, and wondered if her results indicated that we are limited by DAC noise from the ETMX ESD 20 bit DAC.

To test this, I took a look at Jeff Kissel's guardian state, TURN_ON_SUS_DAC_DITHERS, that he created and we have not yet placed in our locking ladder. I used his code in my own script "DAC_dither_chop.py", that would turn on a dither in the ETMX L3 ESD for five minutes, and then off for five minutes so we could compare the effect. This script is currently saved in my home directory, but I will soon move it to the gitcommon labutils.

Using Jeff's code required a few changes, first he uses the LKIN2OSEM matrices, but for L3 we need to use the LKIN2ESD matrix. Also, he set a DAC dither drive of 60,000, which is the same that LLO uses (we referenced this alog and the LLO guardian script for guidance). However, I set up my script to use an amplitude of 600. When running with this drive amplitude, the L3 MASTER OUT RMS was about 77400 counts (21800 pp), which is about a quarter of the DAC range. We believe this was sufficient for the test, and driving with the L2 amplitude would kill our lock.

Sheila and I ran this test in NLN_CAL_MEAS twice (no ADS, PCal or awg lines), once with the ESD at full bias, and again with the ESD at quarter bias. We changed the bias using the same method Sheila describes in her recent alog. We made a comparison plot which is attached here, which uses the OAF clean channel with LSC cleaning engaged. We see similar results to her other alog: full bias has lower noise than 1/4 bias. However, we do not see dependence of the noise on the dac dither. ("Current trace" is a trace with full bias, dac dither off).

Here are the GPS times for our on/off test. All tests ran for 5 minutes:

We have some remaining questions or ideas for what's next:

• Did we run the test correctly? Do we need more DAC dither drive? Again, we used about 1/4 of the range, but we did confirm that our dither line dominated the MASTER OUT RMS
• Should we implement this test with both L3 and L2 DAC dithers? We targeted L3 because we were changing the ESD bias, but there are 20 bit DACs on L1, L2 and L3 of our test masses
  • Craig reminded me that he projected the L2 DAC noise, and that it should not be limiting us, even now
• Sheila's recent bias change test was performed with ADS on, should we redo this test with the ADS lines for better comparison?

Some final notes about implementing our DAC dithers in general:

• I noted that I found an error in Jeff's code about setting up the OSEM/ESD matrix. I have edited his guardian code so that the state will correctly turn on LKIN2OSEM or LKIN2ESD depending on the stage
• We should implement this stage in the guardian ladder so that we are now making use of the DAC dithers, HOWEVER....
• Before we implement this stage, we should think carefully about our drive amplitude. LLO currently runs the dithers on the test mass L2s and BS M2, with a drive of 60000. If we want to run dithers on all of our DACs, we should check the drive amplitudes for each. For the test masses, we could try to implement a different pringle matrix for each stage to account for the different drive amplitudes that each stage will require.
• Currently, the dac dither guardian state will turn on dithers for ALL 20 bit DACs: L1-3 of each test mass, BS M2, and SR2/SRM M2 and M3

***DAC dither code is now in gitcommon/labutils/DAC_dithers