Given the strange status of some of the front ends, we decided to cleanly power cycle all front end computers, IO Chassis, Timing fanouts and IRIG-B units (with the execption of the MSR timing master and IRIG-B which are on UPS).

This was done in the corner station CER, LVEA, EY and MX.

All front ends are now running.

The DAQ was restarted several times. All the EPICS gateways were restarted.

It as noted that VE signals from IOCS MR, LX and LY were unavailable from the power outage to today. We are investigating why.

Daniel provided new INI files for ECAT C1, I have added them to the DAQ and renamed the INI files to the EDCU standard.