This is an update to alog 67291.
For the OMC and ISCEX front-ends new software was installed and new firmware for the timing board was loaded. The later removed the 7.08μs hardware timing delay, whereas the former removed 7 IOP cycles processing delay in the 512KHz OMC.
| Channel | Rate | Delay | Expect | Unit | Comment |
|---|---|---|---|---|---|
| H1:IOP-OMC0_MADC0_TP_CH31 | 512K | 7.72 | 7.6 | μs | 4 cycles |
| H1:IOP-OMC0_ADC_DT_OUT | 512K | 62.2 | 62.0 | μs | 4 cycles + New 8x & 64K/16K |
| H1:OMC-FPGA_DTONE_IN1_DQ | 16K | 52.4 | 52.3 | μs | −3 cycles + New 8x & Std 4x |
| H1:OMC-IPC_DTONE_IN1 | 16K | 64.1 | 64.0 | μs | −3 cycles + New 8x & 64K/16K + IPC delay |
| H1:IOP-ISC_EX_MADC0_TP_CH31 | 64K | 0.01 | 0.0 | μs | none |
| H1:CAL-PCALX_FPGA_DTONE_ADC | 16K | 43.5 | 43.5 | μs | Std 4x |
| H1:IOP-ISC_EX_MADC0_TP_CH30 | 64K | 61.6 | 61.0 | μs | 4 cycles |
| H1:CAL-PCALX_FPGA_DTONE_DAC | 16K | 105.2 | 104.5 | μs | 4 cycles + Std 4x |
For the OMC front-end the reported online DuoTone delay doesn't include the 4 cycles delay and will thus report 0.1μs.
For the DAC DuoTone the expected 4 cycles delay consist of 1 cycle processing delay, since this DuoTone is generated by copying the ADC DuoTone to the DAC, and 3 cycles due to the FIFO on the DAC board. Of course, there can be additional delays due to the board's hardware; we see about 1.6μs.
Tagging a few relevant subsystems who'd be interested in this.
The "4 cycles" in the last 2 rows of the table (DAC delay) should read 4 IOP delays. An ADC cycle is 2-19 s, whereas an IOP delay is 2-16 s.
According to G1501195 the DAC FIFO delay is 2.5 samples (IOP delays) + 1 IOP processing delay. We measure a 4 sample/IOP delay. I assume the difference is the sample-and-hold delay.