Kevin, Dan, Elenna, Camilla, Evan
As part of debugging parametric instability damping, we found that the analog readback of the EY ESD bias voltage has been stuck at zero for the past month. The upper plot in the attachment is the analog readback, and the bottom plot is the digitally requested bias. I hit the HV on/off switch, which seemed to bring the bias back to life.
The PI damping seems much more effective now. It is not clear how we have attained any PI damping at all on EY this past month. I suppose one hypothesis is that we were working off of some other potential difference in the chamber (e.g., typical charge-related potentials of order tens of volts — LHO:68089).
The last time this ESD output was not zero was March 10th see attached, the day we were troubleshooting the ETMX ESD alog 67894. I expect we pressed the HV ON/OFF button during our troubleshooting to compare the two.
Ryan C also spotted something strange in the in-lock charge measurements alog 68089 but I failed to follow up.
We seem to be having PI PLL locking issues since 12:15 on April 3rd. Unclear what changed.
[Daniel Remote]
There is an integrator in the PI PLL FREQ_FILT2 which needed clearing. We are seeing some resonable PLL locks now.
The integrator for mode 24 needed to be cleared mid-lock too, so this should be kept an eye on as the mode was ringing up.