I desgined two new PRCL controller:
First plot compares the open loop gains. The new filter banks are in PRCL2
I chnaged PRCL gain to have a UGF at 30 Hz and started testing the two new controllers.
I successfully enaged the LP100 controller, reducing the PRCL control above 100 Hz.
I caused a lock lss when agaging the Dcntrl. I made the mistake of having this filter at the end of the PRCL filter chain, after an integrator. This new controller increases the DC gain by 10, so I ended up kicking the PRCL control signal. To test it again, the Dcntrl filter module should be moved to PRCL1 at the very input, before the integrator.
The second test of the better PRCL controller succeeded. I mvoed the "Dcntrl" filter bank to FM1 of PRC1, right in front of the integrator. I also engaged the "reg3.4" filter module in PRCL2, to have 10 db more gain at the 3.4 Hz peak, since that's the dominant feature in the PRCL error point RMS.
The new controllers have the effect of
The stability margins for thsi controllers are a bit tighter than the nominal controller, so we need to keep a close eye to the dropping PRCL gain over time
The new controller is now autometd in guardian in the state LOWNOISE_LENGTH_CONTROL. Tested once during the last lock acquisition