WP11227 h1seih16 2nd ADC timing error

Jim, Fil, Erik, Jonathan, EJ, Dave:

This morning Erik worked on the h1seih16 IO Chassis to see what we should try next (timing hardware or PCIe). He found that the second Adnaco backplane link to the front-end computer had status led issues, so we chose to move all the ADC/DAC cards from the second backplane (A2) to the empty third backplane (A3). The ribbon cables are tight, but reach. The updated as-built drawing is attached.

I turned off my program which was clearing the ADC1 TIM errors, any errors will now be latched on.

At time of writing, 3.5 hours in, we have had no errors. But, over the weekend we had a day with only 2 errors total, so we will have to wait at least a couple of days before declaring victory.

Restarts

Quiet maintenance, no model changes, no DAQ restarts

Tue30May2023
LOC TIME HOSTNAME     MODEL/REBOOT
09:22:22 h1seih16     ***REBOOT***
09:23:50 h1seih16     h1iopseih16 
09:38:52 h1seih16     ***REBOOT***
09:40:24 h1seih16     h1iopseih16 
09:40:37 h1seih16     h1hpiham1   
09:40:50 h1seih16     h1hpiham6   
09:41:03 h1seih16     h1isiham6