Reports until 13:35, Tuesday 08 August 2023
H1 CDS
david.barker@LIGO.ORG - posted 13:35, Tuesday 08 August 2023 - last comment - 08:23, Wednesday 09 August 2023(72067)
CDS Maintenance Summary: Tuesday 8th August 2023

WP11359 Consolidated power control IOC software

Erik:

Erik installed new IOC code for the control of Pulizzi and Tripplite network controlled power switches. No DAQ restart was needed.

WP11358 Add new end station Tripplite EPICS channels to the DAQ

Dave:

I modified H1EPICS_CDSACPWR.ini to add the new end station Tripplite control boxes. I found that this file was very much out of date, and only had the MSR Pulizzi channels. I added the missing seven units to the file. DAQ + EDC restart was needed.

WP11357 Add missing ZM4,5 SUSAUX channels to DAQ

Jeff, Rahul, Fil, Marc, Dave:

Jeff discovered that the FM4,5  M1 VOLTMON channels were missing from the SUSAUX model. In this case these are being read by h1susauxh56. It was found that the existing ZM6 channels were actually reading ZM5's channels. h1susauxh56.mdl was modified to:

Change the ADC channels being read by ZM6 from 20-23 to 24-27

Add ZM4 reading ADC channels 16-19

Add ZM5 reading ADC channels 20-23

DAQ Restart was needed.

DAQ Restart

Dave:

Another messy DAQ restart. The sequence was:

  1. Restart the 1-leg
  2. Restart the EDC to include the power control channels
  3. gds1 needed a second restart
  4. When fw1 was back up and had written its first full frame:
  5. Restart the 0-leg
  6. gds0 needed a second restart
  7. After fw0 had written its first full frame, fw1 spontaneously crashed!

This was an interesting data point, last week I restarted the DAQ in the opposite order of 0-leg then 1-leg, and as fw1 was coming back fw0 spontaneously crashed, which in that case resulted in some full frame files not being written by either fw.

Could it be that starting the second fw impacts the first fw's disk access speed (perhaps LDAS gap checker switching between file systems)?

As we have found to be always the case, once the errant fw has crashed once, it does not crash again.

 

Comments related to this report
david.barker@LIGO.ORG - 13:45, Tuesday 08 August 2023 (72068)

DAQ missing full frames GPS times (no overlap between fw0 and fw1 lists) (missing because of crash highlighted)

Scanning directory: 13755...
FW0 Missing Frames [1375554944, 1375555008]
FW1 Missing Frames [1375554752, 1375554816, 1375555072, 1375555136, 1375555200]
 

david.barker@LIGO.ORG - 15:01, Tuesday 08 August 2023 (72078)

This morning new filtermodules were added to h1susauxh56 to readout the ZM4,5 quadrants. The RCG starts new filtermodules in an inactive state, namely with INPUT=OFF, OUTPUT=OFF, GAIN=0.0. It can be a bit time consuming to manually activate the MEDM switches by hand.

I wrote a script to activate new filtermodules, called activate_new_filtermodules. It takes the filtermodule name as its argument.

Here is an example using a h1pemmx filtermodule:

david.barker@opslogin0: activate_new_filtermodule PEM-MX_CHAN_12
H1:PEM-MX_CHAN_12_SW1 => 4
H1:PEM-MX_CHAN_12 => ON: INPUT
H1:PEM-MX_CHAN_12_SW2 => 1024
H1:PEM-MX_CHAN_12 => ON: OUTPUT
H1:PEM-MX_CHAN_12_GAIN => 1.0

 

david.barker@LIGO.ORG - 15:12, Tuesday 08 August 2023 (72079)

------------------- DAQ CHANGES: ------------------------

REMOVED:

No channels removed from the DAQ frame

ADDED:

+8 fast channels added (all at 256Hz)

< H1:SUS-ZM4_M1_VOLTMON_LL_OUT_DQ 4 256
< H1:SUS-ZM4_M1_VOLTMON_LR_OUT_DQ 4 256
< H1:SUS-ZM4_M1_VOLTMON_UL_OUT_DQ 4 256
< H1:SUS-ZM4_M1_VOLTMON_UR_OUT_DQ 4 256
< H1:SUS-ZM5_M1_VOLTMON_LL_OUT_DQ 4 256
< H1:SUS-ZM5_M1_VOLTMON_LR_OUT_DQ 4 256
< H1:SUS-ZM5_M1_VOLTMON_UL_OUT_DQ 4 256
< H1:SUS-ZM5_M1_VOLTMON_UR_OUT_DQ 4 256
 

+112 slow channels added

david.barker@LIGO.ORG - 08:23, Wednesday 09 August 2023 (72092)

Tue08Aug2023
LOC TIME HOSTNAME     MODEL/REBOOT
11:31:41 h1susauxh56  h1susauxh56 <<< Correct ZM6, add ZM4 and ZM5


11:32:59 h1daqdc1     [DAQ] <<< 1-leg restart
11:33:10 h1daqfw1     [DAQ]
11:33:11 h1daqnds1    [DAQ]
11:33:11 h1daqtw1     [DAQ]
11:33:19 h1daqgds1    [DAQ]


11:33:53 h1susauxb123 h1edc[DAQ] <<< EDC restart for CDSACPWR


11:34:25 h1daqgds1    [DAQ] <<< 2nd gds1 restart needed


11:36:06 h1daqdc0     [DAQ] <<< 0-leg restart
11:36:17 h1daqfw0     [DAQ]
11:36:17 h1daqtw0     [DAQ]
11:36:18 h1daqnds0    [DAQ]
11:36:25 h1daqgds0    [DAQ]
11:37:14 h1daqgds0    [DAQ] <<< 2nd gds0 restart needed


11:39:10 h1daqfw1     [DAQ] <<< FW1 crash!!