Since the results from yesterday's quarter bias test (66810) seem inconsistent with Wensday's test (66751), I'm trying a repeat of the test with lines on and off so that we can have the same number of averages for all these configurations.
The SRCL cleaning probably needs retuning because of the ring heater change, we've got pretty high SRCL coherence up to 50Hz right now. This does reproduce that the noise is higher with 1/4 bias, and the result doesn't seem to depend on having the lines on or off. For now I've left the IFO with all the lines back on and full bias, Robert will try some injections in a little while. I'll add a plot to this alog later on.
The first attachment here shows the main result of this test: The noise from 20-40 Hz is higher with the reduced bias, in a similar way to the first test 66751 A secondary thing to note is that we still do not see a broad reduction in noise when the ADS lines are off, as was seen at LLO.
One possible explanation for this increase in noise would be the ESD nonlinearity. We currently don't run with any linearization on the ESD. The ESD actuation is described by Eq 3 in T1700446, and in many other places.
rearranging Eq 3 in terms linear and quadratic with the signal voltage (and dropping the static terms):
F = [2*(gamma - alpha)*V_bias + beta - beta2] * V_signal + (alpha + gamma) V_signal ^2
Aside to understand the gain scaling we needed to match the linear response:
The table in 66751 shows how I adjusted the digital gain in the signal electrode paths to keep the overall loop gain the same. If we reduce V_bias from V_b1 to V_b2 we compensate with digital gain in the signal path to keep the linear force the same (so V_s becomes g*V_s), the gain we need to apply is:
g = [ 2(gamma - alpha) V_b1 + beta - beta 2 ]/ [ 2(gamma - alpha) V_b2 + beta - beta 2 ] (V_b1 = -447V, V_b2 = -124 V)
We can check this against the gain that we needed using some old in lock charge measurements, if the beta terms are both zero we'd see linear gain scaling with the bias (g = 3.6). For the cooefficients measured in 56613 we'd expect g = 1.34 and for the coeficents measured in 38656 we'd expect g = 2.34. So, some up to date in lock charge measurements could help us understand if the gain scaling we see makes sense with this math, but the variation in past measurements has been more than enough to encompass the gain scaling that we saw this time. This means that if we were to run at a reduced bias our ESD actuation strength would probably vary more with the distribution of charge.
Projection of quadratic contribution from ESD:
As we lower the bias and increase the voltage applied to the signal electrodes the quadratic term will become larger and might introduce noise to DARM. The quadratic term in the signal votlage is (alpha + gamma) * V_s ^2. I've added this to the noise budget with the coefficents measured in 56613, using the LVESDAMON channel which is calibrated into volts applied to the ESD (see ESD_Quadratic in budget.py) The second and third attachments show the projections this make with the quarter bias and normal (full bias) configuration. While this does predict upconversion around the calibration and ADS lines with the quarter bias, It doesn't predict well all the extra noise introduced in the quarter bias test. I'm hoping to do a repeat of the quarter bias test with a line injected on the ESD to measure the quadratic term directly rather than infering it from the old charge measurements.
Lance is using the times above for a comparison to recent data, and we noticed that I made a typo above. As the legend in the screenshot indicates, the full bias lines off time is 17:49 UTC 1/14/2023